-
公开(公告)号：US20230292047A1
公开(公告)日：2023-09-14
申请号：US17654719
申请日：2022-03-14
申请人： NXP USA, Inc.
发明人： Surendra Guntur , Joachim Fader , Wolfgang Küchler
摘要： An audio configuration system receives an analyzes ultrawideband radio return signals resulting from one or more pulsed UWB probe signals. The system receives the UWB return signals. The UWB return signals are used to determine a spatial orientation of one or more objects (e.g., one or more seats in a passenger cabin of a vehicle). The system causes audio circuitry to output audio signals according to audio configuration parameters determined by the spatial orientation of the object or objects.
-
公开(公告)号：US10862830B2
公开(公告)日：2020-12-08
申请号：US16222671
申请日：2018-12-17
申请人： NXP USA, INC.
发明人： Naveen Kumar Jain , Joachim Fader , Shreya Singh , Nishant Jain , Anshul Goel
IPC分类号： H04J3/24 , H04L12/861 , H04L7/033 , H04L12/935 , H04L12/939 , H04L12/879 , H04N5/067
摘要： A system and method for real-time data transfer on a system-on-chip (SoC) allows MIPI-CSI (camera serial interface) data received on a first interface to be output on another MIPI-CSI interface without using system memory or delaying the loopback path. The system includes a CSI receiver, a loopback buffer, and a CSI transmitter. The loopback buffer is used for the data transfer between the CSI receiver and the CSI transmitter. The CSI transmitter receives a payload included in a data packet from the CSI receiver by way of the loopback buffer. The CSI receiver communicates a packet header of the data packet to the CSI transmitter. The CSI transmitter reads the payload from the loopback buffer based on the packet header and at least one of a buffer threshold capacity and payload size.
-
公开(公告)号：US20180157848A1
公开(公告)日：2018-06-07
申请号：US15701517
申请日：2017-09-12
申请人： NXP USA, Inc.
发明人： Joachim Fader , Robert Krutsch , Dirk Wendel
CPC分类号： G06F21/602 , G06F11/0727 , G06F11/0751 , G06F11/08 , G06F11/1048 , G06F11/1052 , G06F13/1668
摘要： A system on a chip (SoC) and method of operation are described. A data processor has a processor data word size of p×octets and is configured to handle data items having a data item size which is a non-integer multiple of the processor data word size. A memory controller is configured to write or read data items to a memory as multiples of m×octets. Data can be sent between the data processor and the memory controller on a bus. A data protection code generator is configured to generate a data protection code for a data item generated by the data processor before transmitting the data item and the data protection code over the bus to the memory controller which writes at least one octet including at least a portion of the data item and at least a portion of the data protection code to an address. A data protection code checker is configured to receive a read data protection code and a read data item and to check the read data item for an error using the read data protection code. The memory controller reads at least one octet including at least a portion of the read data item and at least a portion of the read data protection code from a read address.
-
公开(公告)号：US10311241B2
公开(公告)日：2019-06-04
申请号：US15701517
申请日：2017-09-12
申请人： NXP USA, Inc.
发明人： Joachim Fader , Robert Krutsch , Dirk Wendel
摘要： A system on a chip (SoC) and method of operation are described. A data processor has a processor data word size of p×octets and is configured to handle data items having a data item size which is a non-integer multiple of the processor data word size. A memory controller is configured to write or read data items to a memory as multiples of m×octets. Data can be sent between the data processor and the memory controller on a bus. A data protection code generator is configured to generate a data protection code for a data item generated by the data processor before transmitting the data item and the data protection code over the bus to the memory controller which writes at least one octet including at least a portion of the data item and at least a portion of the data protection code to an address. A data protection code checker is configured to receive a read data protection code and a read data item and to check the read data item for an error using the read data protection code. The memory controller reads at least one octet including at least a portion of the read data item and at least a portion of the read data protection code from a read address.
-
公开(公告)号：US20210360090A1
公开(公告)日：2021-11-18
申请号：US15930102
申请日：2020-05-12
申请人： NXP USA, Inc.
摘要： A MIPI CSI-2/D-PHY receiving device is configured to handle being hot plugged to MIPI CSI-2/D-PHY transmitting device. During a hot plugging event, the MIPI CSI-2/D-PHY receiving device has not been initialized by receipt from the MIPI CSI-2/D-PHY transmitting device of a Stop State signal of duration TINIT. Though the MIPI CSI-2/D-PHY transmitting device is already transmitting data associated with a partial frame, the MIPI CSI-2/D-PHY receiving device will not enter into an error or unknown state, and will ignore line start/end and frame end events and drop the data packets associated with the partial frame until a frame start event corresponding to a full frame is received from the MIPI CSI-2/D-PHY transmitting device.
-
-
-
-
搜索结果
5 条记录 (耗时 0.011 秒)
