公开(公告)号：US11747372B2

公开(公告)日：2023-09-05

申请号：US17449776

申请日：2021-10-01

申请人： NXP USA, Inc.

发明人： Xiaoqun Liu ,  Siamak Delshadpour

IPC分类号： G01R31/66 ,  G01R19/165 ,  G01R19/10 ,  H03K5/24

CPC分类号： G01R19/16566 ,  G01R19/10 ,  G01R31/66 ,  H03K5/24

摘要： One example discloses a differential-signal-detection circuit, comprising: an input stage configured to receive a differential input signal and to output a first differential output signal and a second differential output signal; a first comparator coupled to receive the first differential output signal and generate a first comparator output signal; a second comparator coupled to receive the second differential output signal and generate a second comparator output signal; and an output stage configured to receive the first and second comparator output signals and generate a differential-signal-detection signal.

公开(公告)号：US20240154919A1

公开(公告)日：2024-05-09

申请号：US18053172

申请日：2022-11-07

申请人： NXP USA, Inc.

发明人： Siamak Delshadpour ,  Xu Zhang ,  Xiaoqun Liu ,  Xueyang Geng

IPC分类号： H04L49/90

CPC分类号： H04L49/90

摘要： One example discloses a communications circuit, including: a buffer having a buffer input and a buffer output; wherein the buffer includes a first path and a second path; wherein the first path includes, a first resistor coupled to the buffer input; a second resistor coupled to the buffer output; a current source having a first end and a second end; wherein the first resistor and the second resistor are coupled to a mid-point; wherein the first end of the current source is coupled to the mid-point; and wherein the second path includes a capacitor having a first end coupled to the buffer input and a second end coupled to the buffer output.

公开(公告)号：US11863181B2

公开(公告)日：2024-01-02

申请号：US17448515

申请日：2021-09-22

申请人： NXP USA, Inc.

发明人： Xu Zhang ,  Xiaoqun Liu ,  Siamak Delshadpour

IPC分类号： H03K19/0185 ,  H04L25/02

CPC分类号： H03K19/018528 ,  H04L25/0272

摘要： One example discloses a level-shifter circuit, comprising: a pre-driver stage configured to receive differential inputs and generate differential pre-driver outputs; a first output stage coupled to receive the differential pre-driver outputs and generate a single-ended first stage output; a second output stage coupled to receive the differential pre-driver outputs and generate a single-ended second stage output; and wherein the first and second stage outputs together form a differential output.

公开(公告)号：US11846957B1

公开(公告)日：2023-12-19

申请号：US17931384

申请日：2022-09-12

申请人： NXP USA, Inc.

发明人： Xiaoqun Liu ,  Siamak Delshadpour

IPC分类号： G05F1/56 ,  H03K3/013

CPC分类号： G05F1/56 ,  H03K3/013

摘要： One example discloses a signal driver circuit, including: an input configured to receive an input signal; an output configured to transmit an output signal; a low drop-out voltage regulator (LDO) having a regulated voltage output; a set of voltage-modulated amplifiers having a first input coupled to the regulated voltage output, and a second input configured to receive the input signal; wherein the voltage-modulated amplifier is configured to amplify the input signal and transmit an amplified input signal on the output of the signal driver circuit; a de-emphasis controller, including a set of de-emphasis levels; wherein the de-emphasis controller is configured to selectively switch-on a first subset of the set of voltage-modulated amplifiers and switch-off a second subset of the set of voltage-modulated amplifiers based on the de-emphasis levels.

公开(公告)号：US20240223411A1

公开(公告)日：2024-07-04

申请号：US18069664

申请日：2022-12-21

申请人： NXP USA, Inc.

发明人： Xueyang Geng ,  Xu Zhang ,  Xiaoqun Liu ,  Siamak Delshadpour

IPC分类号： H04L25/03 ,  H03F3/45 ,  H03K17/60 ,  H03K17/687

CPC分类号： H04L25/03878 ,  H03F3/45076 ,  H03K17/60 ,  H03K17/687 ,  H03F2203/45458 ,  H03F2203/45496

摘要： Embodiments of equalizers are disclosed. In an embodiment, an equalizer includes a first signal path segment that includes a first plurality of serially connected transistors and current sources, a second signal path segment that includes a second plurality of serially connected transistors and current sources, and at least one termination resistor connected to the first and second signal path segments. The first plurality of serially connected transistors and current sources includes a first current source and a second current source connectable to a reference voltage and a first transistor and a second transistor connected between input terminals of the equalizer and the first and second current sources, where the first signal path segment further includes at least one resistor connected between the first and second current sources.

公开(公告)号：US11368145B1

公开(公告)日：2022-06-21

申请号：US17452413

申请日：2021-10-27

申请人： NXP USA, Inc.

发明人： Xiaoqun Liu ,  Siamak Delshadpour

IPC分类号： H03K5/00 ,  H03K5/1252 ,  H03K19/20 ,  H03K5/24 ,  H03K5/08 ,  H03K5/22

摘要： One example discloses a differential-signal-detection circuit, including: an input stage configured to receive a differential input signal and to output a first differential output signal and a second differential output signal; a first comparator coupled to receive both the first differential output signal and the second differential output signal, and in response generate a first comparator output signal; a second comparator coupled to receive both the first differential output signal and the second differential output signal and generate a second comparator output signal; and an output stage configured to receive the first and second comparator output signals and generate a differential-signal-detection signal; wherein the output stage includes a deglitch circuit configured to attenuate changes in the differential-signal-detection signal during an inter-symbol period of the differential input signal.

公开(公告)号：US20230090949A1

公开(公告)日：2023-03-23

申请号：US17448515

申请日：2021-09-22

申请人： NXP USA, Inc.

发明人： Xu Zhang ,  Xiaoqun Liu ,  Siamak Delshadpour

IPC分类号： H03K19/0185 ,  H04L25/02

摘要： One example discloses a level-shifter circuit, comprising: a pre-driver stage configured to receive differential inputs and generate differential pre-driver outputs; a first output stage coupled to receive the differential pre-driver outputs and generate a single-ended first stage output; a second output stage coupled to receive the differential pre-driver outputs and generate a single-ended second stage output; and wherein the first and second stage outputs together form a differential output.

公开(公告)号：US12068893B2

公开(公告)日：2024-08-20

申请号：US18069664

申请日：2022-12-21

申请人： NXP USA, Inc.

发明人： Xueyang Geng ,  Xu Zhang ,  Xiaoqun Liu ,  Siamak Delshadpour

IPC分类号： H04L25/03 ,  H03F3/45 ,  H03K17/60 ,  H03K17/687

CPC分类号： H04L25/03878 ,  H03F3/45076 ,  H03K17/60 ,  H03K17/687 ,  H03F2203/45458 ,  H03F2203/45496

摘要： Embodiments of equalizers are disclosed. In an embodiment, an equalizer includes a first signal path segment that includes a first plurality of serially connected transistors and current sources, a second signal path segment that includes a second plurality of serially connected transistors and current sources, and at least one termination resistor connected to the first and second signal path segments. The first plurality of serially connected transistors and current sources includes a first current source and a second current source connectable to a reference voltage and a first transistor and a second transistor connected between input terminals of the equalizer and the first and second current sources, where the first signal path segment further includes at least one resistor connected between the first and second current sources.

公开(公告)号：US11573268B1

公开(公告)日：2023-02-07

申请号：US17474209

申请日：2021-09-14

申请人： NXP USA, Inc.

发明人： Siamak Delshadpour ,  Xu Zhang ,  Xiaoqun Liu ,  Kenneth Jaramillo

IPC分类号： H03K19/094 ,  G01R31/317 ,  H03K19/20 ,  H03K19/0185

摘要： Various embodiments relate to a skew detector circuit, including: a logic circuit having two inputs configured to generate a logic 1 output when the two inputs have a logic 0 value and generator a logic 0 output when the two input have a logic 1 value; a first level shifter configured to increase the output of the logic circuit to a higher voltage; a second level shifter configured to increase the output of the first level shifter to a higher voltage; and a voltage regulator configured to produce a first voltage for the logic circuit, a second voltage for the first level shifter, and a third voltage for the second level shift.