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14 条记录 (耗时 0.017 秒)

    Fast startup technique and circuit for a receiver
    2.
    发明授权
    Fast startup technique and circuit for a receiver 有权

    公开(公告)号：US11671092B2

    公开(公告)日：2023-06-06

    申请号：US17475965

    申请日：2021-09-15

    申请人： NXP USA, Inc.

    发明人： Xu Zhang ,  Siamak Delshadpour ,  David Edward Bien

    IPC分类号： H03K17/56 ,  H03K19/20

    CPC分类号： H03K17/56 ,  H03K19/20

    摘要： Various embodiments relate to a receiver, including: a first bias circuit configured to bias a first and second transistor based upon an bias enable signal and a receive enable signal; a first node between the first transistor and a third transistor; a second node between the second transistor and a fourth transistor; and a second bias circuit configured to bias the first node and the second node based upon the bias enable signal, wherein the third transistor is connected to a first differential output and the gate of the third transistor is connected to a first differential input, and wherein the fourth transistor is connected to a second differential output and the gate of the fourth transistor is connected to a second differential input.

    FAST STARTUP TECHNIQUE AND CIRCUIT FOR A RECEIVER
    3.
    发明申请
    FAST STARTUP TECHNIQUE AND CIRCUIT FOR A RECEIVER 有权

    公开(公告)号：US20230079861A1

    公开(公告)日：2023-03-16

    申请号：US17475965

    申请日：2021-09-15

    申请人： NXP USA, Inc.

    发明人： Xu Zhang ,  Siamak Delshadpour ,  David Edward Bien

    IPC分类号： H03K17/56 ,  H03K19/20

    摘要： Various embodiments relate to a receiver, including: a first bias circuit configured to bias a first and second transistor based upon an bias enable signal and a receive enable signal; a first node between the first transistor and a third transistor; a second node between the second transistor and a fourth transistor; and a second bias circuit configured to bias the first node and the second node based upon the bias enable signal, wherein the third transistor is connected to a first differential output and the gate of the third transistor is connected to a first differential input, and wherein the fourth transistor is connected to a second differential output and the gate of the fourth transistor is connected to a second differential input.

    Interface circuit
    4.
    发明授权
    Interface circuit 有权

    公开(公告)号：US10727892B2

    公开(公告)日：2020-07-28

    申请号：US15668611

    申请日：2017-08-03

    申请人： NXP USA, Inc.

    发明人： Xu Zhang ,  Ahmad Yazdi ,  Cornelis Johannes Speelman

    IPC分类号： H02H9/00 ,  H04B1/40 ,  H02H9/04 ,  H01F27/28 ,  G06F13/40 ,  H04L25/02 ,  H03K19/0175

    摘要： One example discloses an interface circuit, including: an inductive coil having a first, second and third terminal; wherein the first terminal is coupled to an external interface port; wherein the second terminal is coupled to a first communication port; wherein the third terminal is coupled to a second communication port; and wherein the inductive coil is configured to attenuate an equivalent capacitance from at least one of the terminals.

    REDRIVER AND RESISTIVE TERMINATION UNIT FOR A REDRIVER
    5.
    发明公开
    REDRIVER AND RESISTIVE TERMINATION UNIT FOR A REDRIVER 审中-公开

    公开(公告)号：US20240171175A1

    公开(公告)日：2024-05-23

    申请号：US17990603

    申请日：2022-11-18

    申请人： NXP USA, Inc.

    发明人： Xu Zhang ,  Siamak Delshadpour

    IPC分类号： H03K17/687 ,  H03H11/02

    CPC分类号： H03K17/6872 ,  H03H11/02

    摘要： Embodiments of redrivers and resistive termination units for redrivers are disclosed. In an embodiment, a resistive termination unit for a redriver includes a resistor connected to an input/output terminal of the redriver, a first switch connected to the resistor and to a supply voltage of the redriver, a second switch connected to the first switch and configured to be turned on or off in response to a change in the supply voltage of the redriver, and a control circuit connected to the first switch through the second switch and configured to generate a control signal for the first switch.

    COMMUNICATIONS CIRCUIT
    6.
    发明公开
    COMMUNICATIONS CIRCUIT 审中-公开

    公开(公告)号：US20240154919A1

    公开(公告)日：2024-05-09

    申请号：US18053172

    申请日：2022-11-07

    申请人： NXP USA, Inc.

    发明人： Siamak Delshadpour ,  Xu Zhang ,  Xiaoqun Liu ,  Xueyang Geng

    IPC分类号： H04L49/90

    CPC分类号： H04L49/90

    摘要： One example discloses a communications circuit, including: a buffer having a buffer input and a buffer output; wherein the buffer includes a first path and a second path; wherein the first path includes, a first resistor coupled to the buffer input; a second resistor coupled to the buffer output; a current source having a first end and a second end; wherein the first resistor and the second resistor are coupled to a mid-point; wherein the first end of the current source is coupled to the mid-point; and wherein the second path includes a capacitor having a first end coupled to the buffer input and a second end coupled to the buffer output.

    Level-shifter
    7.
    发明授权
    Level-shifter 有权

    公开(公告)号：US11863181B2

    公开(公告)日：2024-01-02

    申请号：US17448515

    申请日：2021-09-22

    申请人： NXP USA, Inc.

    发明人： Xu Zhang ,  Xiaoqun Liu ,  Siamak Delshadpour

    IPC分类号： H03K19/0185 ,  H04L25/02

    CPC分类号： H03K19/018528 ,  H04L25/0272

    摘要： One example discloses a level-shifter circuit, comprising: a pre-driver stage configured to receive differential inputs and generate differential pre-driver outputs; a first output stage coupled to receive the differential pre-driver outputs and generate a single-ended first stage output; a second output stage coupled to receive the differential pre-driver outputs and generate a single-ended second stage output; and wherein the first and second stage outputs together form a differential output.

    Low power, wide range, high noise tolerance level shifter
    8.
    发明授权
    Low power, wide range, high noise tolerance level shifter 有权

    公开(公告)号：US10432199B1

    公开(公告)日：2019-10-01

    申请号：US16195414

    申请日：2018-11-19

    申请人： NXP USA, Inc.

    发明人： Xu Zhang

    IPC分类号： H03K19/0185 ,  H03K3/012 ,  H03K19/00 ,  H03K3/037

    摘要： Embodiments for a level shifter are provided, including: a current mirror comprising a reference current transistor and a mirrored current transistor; a pull-down network comprising a first and a second pull-down transistor, wherein the first and second pull-down transistors are respectively connected in series with the reference and mirrored current transistors; a pull-up transistor connected to an intermediate node located between the mirrored current transistor and the second pull-down transistor; a transition control transistor connected to the gate electrode of the reference current transistor; a cut-off transistor connected between the first pull-down transistor and a common negative power supply voltage; and a first and a second inverter connected to the intermediate node, wherein a control node is located between the first and second inverters, and gate electrodes of the pull-up transistor, the transition control transistor, and the cut-off transistor are connected to the control node.