-
公开(公告)号：US08224638B1
公开(公告)日：2012-07-17
申请号：US11650176
申请日：2007-01-05
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F17/5054 , G06F2213/0038
摘要： A method of managing programmable device configuration can include running a server configuration image within the programmable device and storing a different configuration image within a non-volatile memory communicatively linked with the programmable device. Responsive to a switch request sent from the client to the programmable device over the communications link, the different configuration image can be loaded into the programmable device.
摘要翻译： 管理可编程设备配置的方法可以包括在可编程设备内运行服务器配置图像并将不同的配置图像存储在与可编程设备通信地链接的非易失性存储器中。 响应于通过通信链路从客户端发送到可编程设备的切换请求，可以将不同的配置图像加载到可编程设备中。
-
公开(公告)号：US07184946B2
公开(公告)日：2007-02-27
申请号：US10600885
申请日：2003-06-19
申请人： Jonathan B. Ballagh , Nabeel Shirazi , Christopher N. Battson , Michael E. Darnall , Bradley K. Fross
发明人： Jonathan B. Ballagh , Nabeel Shirazi , Christopher N. Battson , Michael E. Darnall , Bradley K. Fross
IPC分类号： G06F9/455
CPC分类号： G06F17/5022
摘要： Method and apparatus for interfacing a high-level modeling system (HLMS) with a reconfigurable hardware platform for co-simulation. In one embodiment a boundary-scan interface is coupled to the HLMS and is configured to translate HLMS-issued commands to signals generally compliant with a boundary-scan protocol, and translate signals generally compliant with a boundary-scan protocol to data compatible with the HLMS. A translator and a wrapper are implemented for configuration of the hardware platform. The translator translates between signals that generally compliant with the boundary-scan protocol and signals that are compliant with a second protocol. A component to be co-simulated is instantiated within the wrapper, and the wrapper transfers signals between the translator and the component.
摘要翻译： 将高级建模系统（HLMS）与用于协同仿真的可重配置硬件平台进行接口的方法和装置。 在一个实施例中，边界扫描接口耦合到HLMS并且被配置为将HLMS发出的命令转换为大体上符合边界扫描协议的信号，并且将通常符合边界扫描协议的信号转换为与HLMS兼容的数据 。 为了配置硬件平台，实现了一个翻译器和一个包装器。 翻译器在通常符合边界扫描协议的信号和符合第二协议的信号之间进行翻译。 要在共模拟的组件在包装器中实例化，并且包装器在转换器和组件之间传送信号。
-
公开(公告)号：US07383478B1
公开(公告)日：2008-06-03
申请号：US11185118
申请日：2005-07-20
申请人： Jonathan B. Ballagh , Alexander Carreira , L. James Hwang , Roger B. Milne , Shay Ping Seng , Nabeel Shirazi
发明人： Jonathan B. Ballagh , Alexander Carreira , L. James Hwang , Roger B. Milne , Shay Ping Seng , Nabeel Shirazi
IPC分类号： G01R31/28
CPC分类号： G01R31/318519 , G01R31/3025 , G01R31/318572 , H04W4/18 , H04W24/00 , H04W92/00
摘要： A programmable logic device (PLD) with a JTAG port, such as an FPGA, is provided with a wireless JTAG adapter to enable wireless communications. Multiple PLDs connected with wireless-to-JTAG adapters can be wirelessly linked in a network to form a large boundary-scan chain serial interface. To communicate with the PLDs having a wireless JTAG port, a host PC running application software is also equipped with a wireless transceiver.
摘要翻译： 具有JTAG端口（例如FPGA）的可编程逻辑器件（PLD）提供有无线JTAG适配器以实现无线通信。 与无线到JTAG适配器连接的多个PLD可以在网络中无线链接以形成大型边界扫描链串行接口。 为了与具有无线JTAG端口的PLD通信，运行应用软件的主机PC还配备有无线收发器。
-
公开(公告)号：US07636653B1
公开(公告)日：2009-12-22
申请号：US11343367
申请日：2006-01-31
CPC分类号： G06F17/5027
摘要： An Ethernet co-simulation interface for use with a software-based simulation tool and a design under test disposed on a programmable device can include a host interface and a network processor. The host interface can execute on a host computing system and facilitate data transfer between the software-based simulation tool and a communication link to the design under test. The network processor can be implemented within the programmable device and facilitate data transfer between the communication link and the design under test. The host interface and the network processor can exchange simulation data formatted as raw Ethernet frames over a point-to-point Ethernet connection.
摘要翻译： 与可编程设备上的基于软件的仿真工具和被测设计一起使用的以太网协同仿真界面可以包括主机接口和网络处理器。 主机接口可以在主机计算系统上执行，并促进基于软件的仿真工具与被测设计的通信链路之间的数据传输。 网络处理器可以在可编程设备内部实现，并促进通信链路和被测设计之间的数据传输。 主机接口和网络处理器可以通过点对点以太网连接交换格式化为原始以太网帧的模拟数据。
-
5.发明授权Systems and methods of co-simulation utilizing multiple PLDs in a boundary scan chain 有权在边界扫描链中利用多个PLD进行协同仿真的系统和方法公开(公告)号：US07747423B1
公开(公告)日：2010-06-29
申请号：US11527841
申请日：2006-09-27
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/86
摘要： Systems and methods of performing co-simulation of a partitioned circuit design using multiple programmable logic devices (PLDs) coupled together to form a boundary scan chain. A host computer is coupled to the scan chain via a programming cable. Resident on the host computer are run-time co-simulation blocks corresponding to blocks from the circuit design, where each block is designated to run on one of the PLDs in the scan chain; a programming cable device driver interfacing with the programming cable; and a proxy component. The proxy component is coupled to all of the run-time co-simulation blocks and the programming cable device driver. Each co-simulation block includes a unique pattern identifier, which is also present in the associated PLD. Using this pattern identifier, data and commands targeted to a specific PLD can be extracted from the scan chain, while ignoring data and commands targeted to other PLDs in the scan chain.
摘要翻译： 使用耦合在一起以形成边界扫描链的多个可编程逻辑器件（PLD）执行分割电路设计的协同仿真的系统和方法。 主机通过编程电缆耦合到扫描链。 主计算机上的驻留是与电路设计中的块对应的运行时协同仿真块，其中每个块被指定为在扫描链中的一个PLD上运行; 与编程电缆接口的编程电缆设备驱动器; 和代理组件。 代理组件耦合到所有运行时协同仿真模块和编程电缆设备驱动程序。 每个共模拟块包括唯一的模式标识符，其也存在于相关联的PLD中。 使用此模式标识符，可以从扫描链中提取针对特定PLD的数据和命令，同时忽略针对扫描链中其他PLD的数据和命令。
-
公开(公告)号：US07707019B1
公开(公告)日：2010-04-27
申请号：US11234529
申请日：2005-09-23
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/86
摘要： A method of co-simulation involving a high level modeling system and an integrated circuit such as, e.g., a programmable logic device (PLD) can include, when writing to at least one input port of the PLD, storing a plurality of commands from a co-simulation engine within a command buffer and, responsive to a send condition, sending the plurality of commands to the PLD as a single transaction. When reading from at least one output port of the PLD, selectively reading from a cache external to the PLD or a memory of the PLD according to a state of cache coherency.
摘要翻译： 涉及高级建模系统和诸如可编程逻辑器件（PLD）的集成电路的协同仿真的方法可以包括在写入PLD的至少一个输入端口时存储来自 协同仿真引擎，并且响应于发送条件，将多个命令作为单个事务发送到PLD。 当从PLD的至少一个输出端口读取时，根据高速缓存一致性的状态选择性地从PLD外部的高速缓存或PLD的存储器读取。
-
7.发明授权公开(公告)号：US08812289B1
公开(公告)日：2014-08-19
申请号：US11732642
申请日：2007-04-04
IPC分类号： G06F9/455 , G06F17/50 , G06F11/36 , G06F17/22 , G06F11/267
CPC分类号： G06F17/5027 , G06F9/455 , G06F11/267 , G06F11/3652 , G06F17/22 , G06F17/5009 , G06F2217/86
摘要： Approaches for simulating an electronic system. In one approach, a software co-simulation platform is configured to produce a first time sequence of values of a plurality of input ports of a design block of the electronic system, consume a second time sequence of values of a plurality of output ports of the design block, and generate access transactions for transferring the first and second sequences of values. The software co-simulation platform generates a plurality of reconfiguration transactions for transferring reconfiguration data for the design block. A PLD is configured to implement a communication block and a control block. The communication block receives the reconfiguration and access transactions from the software co-simulation platform, and the control block reconfigures programmable logic and interconnect resources of the PLD in response to the reconfiguration transactions. The control block also controls the emulation of the design block in response to the access transactions.
摘要翻译： 模拟电子系统的方法。 在一种方法中，软件协同仿真平台被配置为产生电子系统的设计块的多个输入端口的值的第一时间序列，消耗电子系统的多个输出端口的值的第二时间序列 并且生成用于传送第一和第二序列值的访问事务。 软件协同仿真平台生成用于传送用于设计块的重新配置数据的多个重配置事务。 PLD被配置为实现通信块和控制块。 通信块从软件协同仿真平台接收重新配置和访问事务，并且控制块响应于重新配置事务重新配置PLD的可编程逻辑和互连资源。 响应于访问事务，控制块还控制设计块的仿真。
-
8.发明授权Parameterizable compact network processor for low-level communication with an integrated circuit 有权可配置的紧凑型网络处理器，用于与集成电路进行低级通信公开(公告)号：US07590137B1
公开(公告)日：2009-09-15
申请号：US11285708
申请日：2005-11-22
IPC分类号： H04J3/24
CPC分类号： G06F13/385 , G06F2213/3808
摘要： A network processor, disposed on an integrated circuit can include an ingress unit having a dual port block random access memory and an egress unit having a dual port block random access memory. The network processor further can include a network interface configured to write packetized data to the ingress unit and read packetized data from the egress unit as well as a coordination processor configured to coordinate movement of data between the network interface, the ingress unit, and the egress unit.
摘要翻译： 设置在集成电路上的网络处理器可以包括具有双端口块随机存取存储器的入口单元和具有双端口块随机存取存储器的出口单元。 网络处理器还可以包括被配置为将分组化数据写入入口单元并从出口单元读取分组化数据的网络接口以及配置为协调网络接口，入口单元和出口之间的数据移动的协调处理器 单元。
-
公开(公告)号：US07797677B1
公开(公告)日：2010-09-14
申请号：US11268801
申请日：2005-11-08
IPC分类号： G06F9/44
CPC分类号： G06F9/543 , G06F9/541 , G06F17/5054
摘要： A method of passing data among modules of a heterogeneous software system can include identifying a scripted function to be executed within the heterogeneous software system and building a wrapper script by embedding a call to the scripted function and an XTable object associated with the scripted function within the wrapper script. The method further can include executing the wrapper script thereby causing the scripted function to execute and receiving a result from execution of the scripted function.
摘要翻译： 在异构软件系统的模块之间传递数据的方法可以包括识别要在异构软件系统内执行的脚本化功能，以及通过嵌入对脚本化功能的调用和与脚本化功能相关联的XTable对象来构建包装器脚本 包装脚本 该方法还可以包括执行包装器脚本，从而使脚本化功能执行并从脚本化功能的执行接收结果。
-
公开(公告)号：US07346482B1
公开(公告)日：2008-03-18
申请号：US11075340
申请日：2005-03-08
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/86
摘要： Co-simulation of a circuit design includes simulating a first subset of blocks of the circuit design on a software-based co-simulation platform, simulating a second subset of the blocks of the circuit design on a hardware-based co-simulation platform, and maintaining coherency for a memory block of the circuit design between a first representation of data in the memory block on the software-based co-simulation platform and a second representation of the data in the memory block on the hardware-based co-simulation platform. Coherency is maintained by managing mutually exclusive access to the memory block from the first subset of blocks and the second subset of blocks.
摘要翻译： 电路设计的协同仿真包括在基于软件的协同仿真平台上模拟电路设计的块的第一子集，在基于硬件的协同仿真平台上模拟电路设计的块的第二子集，以及 在基于软件的协同仿真平台的存储器块中的数据的第一表示和基于硬件的协同仿真平台的存储器块中的数据的第二表示之间维持电路设计的存储器块的一致性。 通过管理来自块的第一子集和块的第二子集的对存储器块的互斥访问来维持一致性。
-
-
-
-
-
-
-
-
-
搜索结果
51 条记录 (耗时 0.025 秒)
