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    Method of making a semiconductor memory circuit device
    1.
    发明授权
    Method of making a semiconductor memory circuit device 失效
    制造半导体存储器电路器件的方法

    公开(公告)号：US5631182A

    公开(公告)日：1997-05-20

    申请号：US327861

    申请日：1994-10-18

    申请人： Naokatsu Suwanai ,  Hiroyuki Miyazawa ,  Atushi Ogishima ,  Masaki Nagao ,  Kyoichiro Asayama ,  Hiroyuki Uchiyama ,  Yoshiyuki Kaneko ,  Takashi Yoneoka ,  Kozo Watanabe ,  Kazuya Endo ,  Hiroki Soeda

    发明人： Naokatsu Suwanai ,  Hiroyuki Miyazawa ,  Atushi Ogishima ,  Masaki Nagao ,  Kyoichiro Asayama ,  Hiroyuki Uchiyama ,  Yoshiyuki Kaneko ,  Takashi Yoneoka ,  Kozo Watanabe ,  Kazuya Endo ,  Hiroki Soeda

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10844 ,  H01L27/10805 ,  H01L27/10808

    摘要： In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.

    摘要翻译： 在其中每个存储单元由存储单元选择MISFET的串联电路和层叠结构的信息存储电容器构成的半导体存储器电路器件中，在第一区域中存在作为存储单元阵列区域的第一MISFET，其具有 栅极电极和源极和漏极区域; 第一和第二电容电极和延伸到栅电极上的第一绝缘膜上的电介质膜; 位于所述第二容量电极上的第二绝缘膜; 以及位于所述第二绝缘膜上的第一布线，而在作为外围电路区域的第二区域中存在具有栅极电极和源极和漏极区域的第二MISFET; 栅电极上的第一绝缘膜; 第一绝缘膜上的第三绝缘膜; 第三绝缘膜上的第二绝缘膜; 以及在第二绝缘膜上的第二布线。

    Semiconductor memory circuit device and method for fabricating same
    2.
    发明授权
    Semiconductor memory circuit device and method for fabricating same 失效
    半导体存储器电路器件及其制造方法

    公开(公告)号：US5237187A

    公开(公告)日：1993-08-17

    申请号：US799541

    申请日：1991-11-27

    申请人： Naokatsu Suwanai ,  Hiroyuki Miyazawa ,  Atushi Ogishima ,  Masaki Nagao ,  Kyoichiro Asayama ,  Hiroyuki Uchiyama ,  Yoshiyuki Kaneko ,  Takashi Yoneoka ,  Kozo Watanabe ,  Kazuya Endo ,  Hiroki Soeda

    发明人： Naokatsu Suwanai ,  Hiroyuki Miyazawa ,  Atushi Ogishima ,  Masaki Nagao ,  Kyoichiro Asayama ,  Hiroyuki Uchiyama ,  Yoshiyuki Kaneko ,  Takashi Yoneoka ,  Kozo Watanabe ,  Kazuya Endo ,  Hiroki Soeda

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10844 ,  H01L27/10805 ,  H01L27/10808

    摘要： In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region, which is a memory cell array region, a first MISFET having a gate electrode and source and drain regions; first and second capacitor electrodes and a dielectric film extended over a first insulating film and over the gate electrode; a second insulating film disposed on the second capacitor electrode; a third insulating film interposed between the first insulating film and first capacitor electrode; and a first wiring positioned on the second insulating film. In a second region of the device, which is a peripheral circuit region, there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a second insulating film on a third insulating film, the third insulating film being interposed between the first and second insulating films; and a second wiring on the second insulating film. The second wiring is formed by the same level conductor layer as that forming the first wiring. Similarly, the first through third insulating films of the first region are correspondingly associated with the first through third insulating films of the second region, respectively.

    摘要翻译： 在其中每个存储单元由存储单元选择MISFET的串联电路和层叠结构的信息存储电容器构成的半导体存储器电路器件中，存在作为存储单元阵列区域的第一区域，第一 MISFET具有栅极电极和源极和漏极区域; 第一和第二电容器电极以及在第一绝缘膜上并在栅电极上方延伸的电介质膜; 设置在所述第二电容器电极上的第二绝缘膜; 介于所述第一绝缘膜和所述第一电容器电极之间的第三绝缘膜; 以及位于第二绝缘膜上的第一布线。 在作为外围电路区域的器件的第二区域中，存在具有栅极电极和源极和漏极区域的第二MISFET， 栅电极上的第一绝缘膜; 在第三绝缘膜上的第二绝缘膜，所述第三绝缘膜介于所述第一和第二绝缘膜之间; 以及在第二绝缘膜上的第二布线。 第二布线由与形成第一布线的层相同的导体层形成。 类似地，第一区域的第一至第三绝缘膜分别与第二区域的第一至第三绝缘膜相关联。

    Method of making a semiconductor memory circuit device
    4.
    发明授权
    Method of making a semiconductor memory circuit device 失效
    制造半导体存储器电路器件的方法

    公开(公告)号：US5389558A

    公开(公告)日：1995-02-14

    申请号：US104014

    申请日：1993-08-10

    申请人： Naokatsu Suwanai ,  Hiroyuki Miyazawa ,  Atushi Ogishima ,  Masaki Nagao ,  Kyoichiro Asayama ,  Hiroyuki Uchiyama ,  Yoshiyuki Kaneko ,  Takashi Yoneoka ,  Kozo Watanabe ,  Kazuya Endo ,  Hiroki Soeda

    发明人： Naokatsu Suwanai ,  Hiroyuki Miyazawa ,  Atushi Ogishima ,  Masaki Nagao ,  Kyoichiro Asayama ,  Hiroyuki Uchiyama ,  Yoshiyuki Kaneko ,  Takashi Yoneoka ,  Kozo Watanabe ,  Kazuya Endo ,  Hiroki Soeda

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10844 ,  H01L27/10805 ,  H01L27/10808

    摘要： In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.

    摘要翻译： 在其中每个存储单元由存储单元选择MISFET的串联电路和层叠结构的信息存储电容器构成的半导体存储器电路器件中，在第一区域中存在作为存储单元阵列区域的第一MISFET，其具有 栅极电极和源极和漏极区域; 第一和第二电容电极和延伸到栅电极上的第一绝缘膜上的电介质膜; 位于所述第二容量电极上的第二绝缘膜; 以及位于所述第二绝缘膜上的第一布线，而在作为外围电路区域的第二区域中存在具有栅极电极和源极和漏极区域的第二MISFET; 栅电极上的第一绝缘膜; 第一绝缘膜上的第三绝缘膜; 第三绝缘膜上的第二绝缘膜; 以及在第二绝缘膜上的第二布线。