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公开(公告)号：US06331967B1
公开(公告)日：2001-12-18
申请号：US09522075
申请日：2000-03-09
IPC分类号： G11B700
CPC分类号： G11B19/247
摘要： In a device for controlling rotation of a disk, if a determination is made that a signal is not normally detected by a pre-pit-region detection circuit, an error signal is obtained from a pulse generator to control the rotation of the disk. If a determination is made that a signal is normally detected by the pre-pit-region detection circuit and if the synchronizing signals are not normally detected at predetermined intervals, an error signal is obtained from the wobble signal so that the rotations of the disk are controlled. If a determination is made that synchronizing signals are detected by the pre-pit-region detection circuit at predetermined intervals, an error signal is obtained from clocks synchronized with the reproduced signal generated by the PLL circuit so that rotations of the disk are controlled.
摘要翻译： 在用于控制盘的旋转的装置中，如果确定信号未被预凹坑区域检测电路正常检测到，则从脉冲发生器获得误差信号以控制盘的旋转。 如果通过预凹坑区域检测电路确定正常地检测到信号，并且如果以预定的间隔正常地检测到同步信号，则从摆动信号获得误差信号，使得盘的旋转为 受控。 如果确定预定间隔检测电路以预定间隔检测同步信号，则从与PLL电路产生的再现信号同步的时钟获得误差信号，从而控制盘的旋转。
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公开(公告)号：US06259662B1
公开(公告)日：2001-07-10
申请号：US09210588
申请日：1998-12-14
IPC分类号： G11B700
CPC分类号： G11B19/28
摘要： When a detected value of the signal processing speed from a frequency comparator is larger than a prescribed value input from an input terminal, the rotation control of a disk is switched from constant linear velocity control to constant angular velocity control using an error signal from an arithmetic unit. Alternatively, when a detected value of the rotational velocity from a frequency comparator is larger than a prescribed value input form an input terminal, the rotation control of the disk is switched from the constant angular velocity control into the constant linear velocity control.
摘要翻译： 当来自频率比较器的信号处理速度的检测值大于从输入端子输入的规定值时，使用来自算术的误差信号将盘的旋转控制从恒定线速度控制切换到恒定角速度控制 单元。 或者，当来自频率比较器的旋转速度的检测值大于从输入端子输入的规定值时，盘的旋转控制从恒定角速度控制切换到恒定线速度控制。
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公开(公告)号：US06421308B1
公开(公告)日：2002-07-16
申请号：US09241411
申请日：1999-02-02
IPC分类号： G11B2010
CPC分类号： G11B27/36 , G11B7/00718 , G11B7/00745 , G11B20/1833 , G11B27/24 , G11B27/3027 , G11B2220/216 , G11B2220/2575
摘要： For recording data on and reproducing data from an optical disk of a single spiral land/groove configuration, a header detector detects header regions on the optical disk, a PID error detector judges whether the address information read from the header regions is erroneous, using error detection codes, and detects the number of errors per sector. An error count comparator compares the number of errors per sector with a predetermined value, and a state judging circuit identifies the state of the optical disk device by causing transition to a higher or lower state according to the output of the error count comparator. The recording and reproduction are controlled according to the state thus identified.
摘要翻译： 为了在单个螺旋纹/纹槽配置的光盘上记录数据和再现数据，标题检测器检测光盘上的标题区，PID错误检测器判断从标题区读出的地址信息是否错误，使用错误 检测代码，并检测每个扇区的错误数。 误差计数比较器将每个扇区的误差数与预定值进行比较，状态判断电路根据误差计数比较器的输出，通过转变到更高或更低的状态来识别光盘装置的状态。 根据所识别的状态来控制记录和再现。
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公开(公告)号：US06275878B1
公开(公告)日：2001-08-14
申请号：US09239994
申请日：1999-01-29
IPC分类号： G06F306
CPC分类号： G11B20/1883 , G11B20/10 , G11B20/1833 , G11B27/3027 , G11B2220/20 , G11B2220/216 , G11B2220/2575
摘要： A data recorder for recording data onto a record medium on which a sync signal is inserted at a given interval, has a sequence controller, wherein, after receiving the command from the system controller which triggers an initiation of a recording operation, the sequence controller activates the first encoder in response to a leading end signal of the encoded block from the sync signal set-up section, activates the first encoder and the second encoder in response to a leading end signal of the next encoded block, and activates the first encoder, the second encoder and the data reader in response to a leading end signal of the next following encoded block, and wherein, during the absence of the command from the system controller which triggers an initiation of a recording operation, the sequence controller deactivates the first encoder in response to a leading end signal of an encoded block from the sync signal set-up section, deactivates the first encoder and the second encoder in response to a leading end signal of the next encoded block, and deactivates the first encoder, the second encoder and the data reader in response to a leading end signal of the next following encoded block.
摘要翻译： 用于将数据记录到以给定间隔插入同步信号的记录介质上的数据记录器具有序列控制器，其中在从系统控制器接收到触发记录操作开始的命令之后，序列控制器激活 第一编码器响应于来自同步信号建立部分的编码块的前端信号，响应于下一编码块的前端信号激活第一编码器和第二编码器，并激活第一编码器， 所述第二编码器和所述数据读取器响应于所述下一个后续编码块的前端信号，并且其中，在不存在触发记录操作开始的系统控制器的命令的情况下，所述序列控制器使所述第一编码器 响应于来自同步信号设置部分的编码块的前端信号，在第一编码器和第二编码器的响应中停用 nse到下一个编码块的前导信号，并且响应于下一个后续编码块的前导信号去激活第一编码器，第二编码器和数据读取器。
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公开(公告)号：US6118742A
公开(公告)日：2000-09-12
申请号：US058844
申请日：1998-04-13
IPC分类号： G11B19/28 , G11B19/247 , G11B27/22
CPC分类号： G11B19/247
摘要： If a determination is made that a signal is not normally detected by the pre-pit-region detection circuit 53, an error signal is obtained from a pulse generator 58 to control the rotations of the disk 50. If a determination is made that a signal is normally detected by the pre-pit-region detection circuit 53 and if the synchronizing signals are not normally detected at predetermined intervals, an error signal is obtained from the wobble signal so that the rotations of the disk 50 are controlled. If a determination is made that synchronizing signals are detected by the pre-pit-region detection circuit 53 at predetermined intervals, an error signal is obtained from clocks synchronized with the reproduced signal generated by the PLL circuit 54 so that rotations of the disk 50 are controlled.
摘要翻译： 如果确定信号未被预凹坑区域检测电路53正常检测到，则从脉冲发生器58获得误差信号以控制盘50的旋转。如果确定信号 通常由预凹坑区域检测电路53检测到，并且如果以预定间隔不正常地检测到同步信号，则从摆动信号获得误差信号，从而控制盘50的旋转。 如果确定了预定间隔检测电路53以预定间隔检测到同步信号，则从与PLL电路54产生的再现信号同步的时钟获得误差信号，使得盘50的旋转为 受控。
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6.发明授权
公开(公告)号：US5852805A
公开(公告)日：1998-12-22
申请号：US621615
申请日：1996-03-26
CPC分类号： G10L19/005 , H04B1/665
摘要： An MPEG audio decoder has an irregular-pattern processing circuit for detecting irregular patterns in the bit stream input to the decoder, and altering these irregular patterns, or altering data or signals derived from these irregular patterns, so that the irregular patterns do not cause annoying defects in the audio signal output from the decoder. The alteration may take the form of replacement by a minimum value, or interpolation of a preceding value.
摘要翻译： MPEG音频解码器具有不规则图案处理电路，用于检测输入到解码器的比特流中的不规则图案，并改变这些不规则图案，或改变从这些不规则图案导出的数据或信号，使得不规则图案不引起讨厌 从解码器输出的音频信号中的缺陷。 该变更可以以最小值的替换形式或先前值的插值。
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公开(公告)号：US5694522A
公开(公告)日：1997-12-02
申请号：US596426
申请日：1996-02-02
CPC分类号： G10L19/0208 , H04B1/667 , G10L25/27
摘要： A sub-band audio signal synthesizer produces a digital audio signal from a sub-band coded audio signal having a predetermined number of sub-bands. A memory stores predetermined samples. A memory controller controls read and write operations of the memory. An adder adds the signal read out of the memory to a new window signal produced on the sub-band coded audio signal to synthesize a digital audio signal. A buffer memory stores and outputs the synthesized digital audio signal and an interpolation signal of the digital audio signal. During normal synthesis, the memory-controller cyclically reads the samples stored in the memory beginning from an address shifted by a predetermined number of samples every time a new cycle of reading is started. The memory-controller writes a result of the addition by the adder back into the memory, thereby producing cumulatively added samples of the window signals. The output circuit outputs, from among the cumulatively added samples, a predetermined number of samples which have been subjected to a predetermined number of cumulative additions, the sample being outputted every time the addition is performed. During interpolation, the memory-controller prevents the result of the addition from being written into the memory, and repeatedly reads the cumulatively added samples from the memory. The output circuit outputs the cumulatively added samples read from the memory as the interpolation signal of the digital audio signal.
摘要翻译： 子带音频信号合成器从具有预定数量的子带的子带编码音频信号产生数字音频信号。 存储器存储预定样本。 存储器控制器控制存储器的读写操作。 加法器将从存储器读出的信号添加到在子带编码音频信号上产生的新窗口信号以合成数字音频信号。 缓冲存储器存储并输出合成的数字音频信号和数字音频信号的内插信号。 在正常合成期间，存储器控制器每次开始读取新的循环时，循环地读取存储在存储器中的样本，从开始移动预定数量样本的地址开始。 存储器控制器将加法器的加法结果写入存储器，从而产生累加的窗口信号的采样。 输出电路从累加的样本中输出预定数量的累积加法的样本数，每次执行加法时都输出样本。 在插补期间，存储器控制器防止将加法结果写入存储器，并从存储器中反复读取累加的样本。 输出电路输出从存储器读出的累加样本作为数字音频信号的插值信号。
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