Non-volatile semiconductor memory device and semiconductor disk device
    2.
    发明授权
    Non-volatile semiconductor memory device and semiconductor disk device 失效
    非易失性半导体存储器件和半导体磁盘器件

    公开(公告)号:US06813185B2

    公开(公告)日:2004-11-02

    申请号:US10786007

    申请日:2004-02-26

    IPC分类号: G11C1604

    摘要: A non-volatile memory device is provided which includes a flash memory having a plurality of banks and a bank selection register which can take on states at least equal in number to the number of banks. The bank selection register outputs a signal to point to one of the banks based upon one of the states of the bank selection register. A controller is also provided having a plurality of data buffers corresponding, respectively, to the banks. In addition to word lines, bit lines and memory cells, each bank includes a data register to temporarily hold data to be written to the memory cells. The controller transmits data in the data buffer to the data register of the pointed to bank, while the flash memory writes data held in the data register to the memory cells of another one of the banks.

    摘要翻译: 提供了一种非易失性存储器件,其包括具有多个存储体的闪速存储器和可选择与存储体数目至少相等的状态的存储体选择寄存器。 存储体选择寄存器基于存储体选择寄存器的一种状态输出指向一组存储体的信号。 还提供了具有分别对应于银行的多个数据缓冲器的控制器。 除了字线,位线和存储单元之外,每个存储体都包括一个数据寄存器,用于临时保存要写入存储单元的数据。 控制器将数据缓冲器中的数据发送到指向库的数据寄存器,而闪存将数据寄存器中保存的数据写入另一个存储体的存储单元。

    Non-volatile semiconductor memory device and semiconductor disk device
    3.
    发明授权
    Non-volatile semiconductor memory device and semiconductor disk device 有权
    非易失性半导体存储器件和半导体磁盘器件

    公开(公告)号:US06714452B2

    公开(公告)日:2004-03-30

    申请号:US10205426

    申请日:2002-07-26

    IPC分类号: G11C1604

    摘要: A non-volatile semiconductor memory device is capable of having its individual banks controlled separately from the outside, and a semiconductor disk device is capable of proceeding immediately to the next writing to a bank of non-volatile semiconductor memory device which has become ready. Each bank has the independent write operation of data from its data register to memory cells, enabling the transfer of data from the outside to the data register of the bank even during the write operation of other bank from the data register to memory cells thereof.

    摘要翻译: 非易失性半导体存储器件能够使其单独的存储体与外部分开控制,并且半导体盘装置能够立即进行下一次写入已经准备就绪的非易失性半导体存储器件组。 每个存储体具有从其数据寄存器到存储器单元的数据的独立写入操作,使得即使在其他存储体从数据寄存器写入其存储器的存储单元的写入操作期间也能够将数据从外部传送到存储体的数据寄存器。

    Programming method of nonvolatile semiconductor memory device

    公开(公告)号:US06636437B2

    公开(公告)日:2003-10-21

    申请号:US10260407

    申请日:2002-10-01

    IPC分类号: G11C1604

    CPC分类号: G11C11/5628

    摘要: In a nonvolatile semiconductor memory device capable of the storage of multivalued data, fast writing can be realized with high reliability. In such a nonvolatile semiconductor memory device for storing multivalued information in one memory cell by setting a plurality of threshold voltages of data, writing of data having one threshold voltage that is the remotest to an erased state is performed prior to writing of the data having the other threshold voltages (write #1). Writing of the data having the other threshold voltages is then sequentially performed within groups of threshold voltages, starting from the nearer threshold voltage to the erased state within each group. When writing each of the data having the other threshold voltages, writing of the data is performed to a memory cell beginning with those groups having the remoter threshold voltages from the erased state.

    Nonvolatile semiconductor memory device
    6.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号:US06243290B1

    公开(公告)日:2001-06-05

    申请号:US09645878

    申请日:2000-08-25

    IPC分类号: G11C1604

    摘要: The present invention provides a nonvolatile semiconductor memory device for multilevel data storage that simultaneously carries out programming of multilevel data and subsequent verification at a high programming throughput. For this purpose, the present device includes a circuit 6 to hold programming data when programming is executed, a circuit 7 to generate timing signals to set up level-specific phases of verifying multilevel programming data during a verification period, a circuit 2 to increase stepwise the selected word line voltage during verification in accordance with the above timing signals, a circuit 4 to select target memory cells 1 for verification, depending on the data retrieved from the latch in accordance with the above timing signals, and verify whether the selected memory cells have been programmed on threshold voltage level, according to the energized or de-energized state thereof, and a circuit 5 to supply programming bias to the bit line to program data into insufficiently programmed memory cells, according to the verify results.

    摘要翻译: 本发明提供了一种用于多级数据存储的非易失性半导体存储器件,其以高编程吞吐量同时执行多级数据的编程和后续验证。为此,本设备包括:当执行编程时保存编程数据的电路6, 电路7,用于产生定时信号,以在验证期间建立验证多电平编程数据的电平特定相位;电路2,根据上述定时信号在校验期间逐步增加所选择的字线电压;电路4,用于选择 取决于根据上述定时信号从锁存器检索的数据,并且根据其通电或去激励状态来验证所选择的存储器单元是否已经被设置在阈值电压电平上,以及 一个向位线提供编程偏置以将数据编程为不足的电路5 根据验证结果,编程好的内存单元。

    Non-volatile semiconductor memory device and semiconductor disk device
    8.
    发明授权
    Non-volatile semiconductor memory device and semiconductor disk device 有权
    非易失性半导体存储器件和半导体磁盘器件

    公开(公告)号:US07359244B2

    公开(公告)日:2008-04-15

    申请号:US11492929

    申请日:2006-07-26

    IPC分类号: G11C16/04

    摘要: A non-volatile memory device is provided which includes a flash memory having a plurality of banks and a bank selection register which can take on states at least equal in number to the number of banks. The bank selection register outputs a signal to point to one of the banks based upon one of the states of the bank selection register. A controller is also provided having a plurality of data buffers corresponding, respectively, to the banks. In addition to word lines, bit lines and memory cells, each bank includes a data register to temporarily hold data to be written to the memory cells. The controller transmits data in the data buffer to the data register of the pointed to bank, while the flash memory writes data held in the data register to the memory cells of another one of the banks.

    摘要翻译: 提供了一种非易失性存储器件,其包括具有多个存储体的闪速存储器和可选择与存储体数目至少相等的状态的存储体选择寄存器。 存储体选择寄存器基于存储体选择寄存器的一种状态输出指向一组存储体的信号。 还提供了具有分别对应于银行的多个数据缓冲器的控制器。 除了字线,位线和存储单元之外,每个存储体都包括一个数据寄存器,用于临时保存要写入存储单元的数据。 控制器将数据缓冲器中的数据发送到指向库的数据寄存器,而闪存将数据寄存器中保存的数据写入另一个存储体的存储单元。