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1.发明授权Apparatus for generating an arbitrary parameter curve represented as an n-th order Bezier curve 失效用于产生以n阶贝塞尔曲线表示的任意参数曲线的装置
公开(公告)号：US5241654A
公开(公告)日：1993-08-31
申请号：US917685
申请日：1992-07-22
申请人： Naoyuki Kai , Masahide Ohhashi , Ichiro Nagashima
发明人： Naoyuki Kai , Masahide Ohhashi , Ichiro Nagashima
IPC分类号： G06T11/20
CPC分类号： G06T11/203
摘要： Coordinate values of control points of a given Bezier curve are stored in a register, the contents of the register are supplied to a determination circuit to determine whether a distance between adjacent control points can further be bisected into two parts. If bisecting processing can be performed, the contents of the register are supplied to a bisection circuit, the Bezier curve is subdivided into two parts to generate new Bezier curves, and control point data of one of the new Bezier curves is applied to a stack memory and that of the other new Bezier curve is sent to the register. The contents of the register are checked by the determination circuit each time the contents of the register are updated.
摘要翻译： 给定贝塞尔曲线的控制点的坐标值存储在寄存器中，寄存器的内容被提供给确定电路，以确定相邻控制点之间的距离是否可进一步分成两部分。 如果可以进行平分处理，则将寄存器的内容提供给平分电路，将贝塞尔曲线细分为两部分以生成新的贝塞尔曲线，并将新的贝塞尔曲线之一的控制点数据应用于堆栈存储器 而另一个新的贝塞尔曲线的曲线被发送到寄存器。 每当更新寄存器的内容时，由确定电路检查寄存器的内容。
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公开(公告)号：US5016001A
公开(公告)日：1991-05-14
申请号：US302709
申请日：1989-01-27
申请人： Tsutomu Minagawa , Masahide Ohhashi , Naoyuki Kai
发明人： Tsutomu Minagawa , Masahide Ohhashi , Naoyuki Kai
摘要： A pattern data generating system comprises first and second bit map memories, a first control block for sequentially generating points corresponding to the boundaries of a closed curve in response to changes dx and dy along x and y directions, and writing the points in the first bit map memory, a second control block for sequentially generating points, which are required to paint an area enclosed by the closed curve, on the basis of the changes dx and dy, in accordance with a predetermined rule, and writing the points in the second bit map memory, a third control block for, if w (w is a positive integer) points b0, b1, . . . , b(w-2), and b(w-1) are present on a single scan line provided that one direction is set to be a scan direction on the second bit map memory, sequentially writing EXOR data of the points b0, b1, . . . , b(j-1) (j is not less than 0 and less than w) at positions corresponding to points b(j), and a fourth control block for obtaining pattern data by final filling or painting in which an arithmetic operation (e.g., logical OR or logical AND) of data of an arbitrary point in the first bit map memory with data of a corresponding point in the second bit map memory which stores the EXOR data is performed.
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公开(公告)号：US5029106A
公开(公告)日：1991-07-02
申请号：US302711
申请日：1989-01-27
申请人： Naoyuki Kai , Masahide Ohhashi , Tsutomu Minagawa
发明人： Naoyuki Kai , Masahide Ohhashi , Tsutomu Minagawa
摘要： A pattern data generating system has a processor for writing in a bit map memory, on the basis of input data, points of all lines to be filled or painted along a scan direction which is one direction on the bit map memory. This writing is performed such that a point on each line is written as one of the two end points of the line thereof while a point, offset by one point in the scan direction, is written as the other of the two end points of the line. The pattern data generating system also has a pattern data generating circuit for, if w (w is a positive integer) points b0, b1, . . . , b(w-2), and b(w-1) are present on one scan line, writing EXOR of data of points b0, b1, . . . , b(j-1) at positions corresponding to points b(j) (j is not less than 0 and less than w). Similar EXOR data writing is performed by the pattern data generating circuit for all the scan lines. Then, pattern data, in which the area surrounded by the closed curve is filled or painted, is obtained.
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公开(公告)号：US5018147A
公开(公告)日：1991-05-21
申请号：US301675
申请日：1989-01-26
申请人： Naoyuki Kai , Masahide Ohhashi , Tsutomu Minagawa
发明人： Naoyuki Kai , Masahide Ohhashi , Tsutomu Minagawa
CPC分类号： G06F11/10
摘要： A bit mask generator comprises partial mask generators for generating partial mask data corresponding to a plurality of blocks obtained by dividing input data, and parity correction circuits for correcting the partial mask data in accordance with a parity input and generating parity outputs. Each of the partial mask generators includes a plurality of first exclusive OR gates each of which receives bit data of a corresponding block as one input and input data of an LSB (Least Significant Bit) or an output of a lower-bit first exclusive OR gate as the other input. Each of the parity correction circuits includes a plurality of second exclusive OR gates each of which receives as one input the partial mask data generated by the partial mask generator of a corresponding block and as the other input a parity generated by a lower-bit parity correction circuit. An output from each second exclusive OR gate is generated as mask data of the corresponding block, and an output from the MSB (Most Significant Bit) second exclusive OR gate is generated as the parity.
摘要翻译： 位掩码生成器包括用于产生对应于通过分割输入数据获得的多个块的部分掩码数据的部分掩码生成器和用于根据奇偶校验输入校正部分掩码数据的奇偶校正电路，并产生奇偶校验输出。 每个部分掩模生成器包括多个第一异或门，每个第一异或门接收相应块的位数据作为一个输入，并输入LSB（最低有效位）的数据或低位第一异或门的输出 作为其他输入。 每个奇偶校正电路包括多个第二异或门，每个第二异或门作为一个输入接收由相应块的部分掩码生成器产生的部分掩码数据，并且作为另一个输入由低位奇偶校验产生的奇偶校验 电路。 生成来自每个第二异或门的输出作为相应块的掩码数据，并且生成来自MSB（最高有效位）第二异或门的输出作为奇偶校验。
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公开(公告)号：US4970688A
公开(公告)日：1990-11-13
申请号：US397837
申请日：1989-08-24
CPC分类号： G06F7/00
摘要： A memory device having an operating function includes a memory cell array, a register, and a logical opeation circuit. The memory cell array has memory cells arranged in a matrix form of m rows .times.n columns. Data readout or write-in operation with respect to the memory cell array is effected in the unit of n bits of one row. The register has a bit width corresponding to one row of the memory cell array. Data of one row is read out from the memory cell array and is processed by the logical operation circuit together with data stored in the register. The result of operation is written into a desired row of the memory cell array. The memory cell array, register, and logical operation circuit are formed in the same integrated circuit, thus permitting processing such as picture element processing to be effected inside the integrated circuit, without the need to use an external data bus.
摘要翻译： 具有操作功能的存储器件包括存储单元阵列，寄存器和逻辑运算电路。 存储单元阵列具有以m行×n列的矩阵形式排列的存储单元。 相对于存储单元阵列的数据读出或写入操作以一行的n位为单位进行。 寄存器具有对应于存储单元阵列的一行的位宽度。 一行的数据从存储单元阵列中读出，并由逻辑运算电路与存储在寄存器中的数据一起处理。 操作结果写入存储单元阵列的所需行。 存储单元阵列，寄存器和逻辑运算电路形成在相同的集成电路中，从而允许在集成电路内实现诸如图像元素处理的处理，而不需要使用外部数据总线。
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公开(公告)号：US5386502A
公开(公告)日：1995-01-31
申请号：US123849
申请日：1993-09-09
申请人： Tsutomu Minagawa , Naoyuki Kai , Masahide Ohhashi
发明人： Tsutomu Minagawa , Naoyuki Kai , Masahide Ohhashi
CPC分类号： G06T11/40
摘要： A painting pattern generation system for painting interior areas enclosed by outlines indicated by outline data and flag data. This includes a first memory for storing outline data, a second memory for storing flag data, and an operational circuit for reading out the outline data. The flag data in the first and the second memories performs a logical exclusive OR operation on adjacent items of the flag data in the second memory in a scan line direction, and performs an OR operation between the result of the logical exclusive OR operation and the outline data in the first memory in all of the scan line directions. Thus obtaining the painted pattern data, and a writing circuit for writing the painted pattern data obtained by the operational circuit to overlap it with subsequent outline data in the first memory.
摘要翻译： 用于绘制由轮廓数据和标志数据表示的轮廓所包围的内部区域的绘画图案生成系统。 这包括用于存储轮廓数据的第一存储器，用于存储标志数据的第二存储器和用于读出轮廓数据的操作电路。 第一和第二存储器中的标志数据在扫描线方向上对第二存储器中的标志数据的相邻项执行逻辑异或运算，并且执行逻辑异或运算的结果与轮廓 在所有扫描线方向上的第一个存储器中的数据。 从而获得绘制的图案数据，以及写入电路，用于写入由操作电路获得的绘制图案数据以与第一存储器中的后续轮廓数据重叠。
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公开(公告)号：US4498178A
公开(公告)日：1985-02-05
申请号：US467297
申请日：1983-02-17
申请人： Masahide Ohhashi
发明人： Masahide Ohhashi
CPC分类号： H03M13/15 , G11B20/1833
摘要： A data error correction circuit is provided, which receives input data having check bit data added thereto, the input data being divided by a generator polynomial G(x) in terms of the modulo 2 and multiplied by a correction polynomial M(x) in terms of modulo 2. An error in the input data is detected and corrected in accordance with contents of a syndrome obtained by these operations. The data error correction circuit includes a latch circuit and a presettable data input circuit. Data from the presettable data input circuit is divided by the generator polynomial G(x) in terms of the modulo 2, and remainder bit data obtained thereby is stored in the latch circuit as the correction polynomial M(x).
摘要翻译： 提供了一种数据纠错电路，其接收具有添加到其中的校验位数据的输入数据，该输入数据按照模2被乘以生成多项式G（x）并乘以校正多项式M（x） 根据通过这些操作获得的综合征的内容来检测和校正输入数据中的错误。 数据纠错电路包括一个锁存电路和一个可预置的数据输入电路。 来自可预置数据输入电路的数据以模2除以生成多项式G（x），并且由此得到的剩余位数据作为校正多项式M（x）存储在锁存电路中。
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公开(公告)号：US4573137A
公开(公告)日：1986-02-25
申请号：US414833
申请日：1982-09-03
申请人： Masahide Ohhashi
发明人： Masahide Ohhashi
CPC分类号： G06F7/507
摘要： In an adder circuit in which the input data is divided into a plurality of bit blocks each consisting of a plurality of bits for parallel data processing, two adder sections with the carry inputs thereto respectively set to logic "0" and "1" are provided for each of the blocks other than the LSB block. The sum and carry outputs from each section in each block are commonly connected through a gate circuit, which is controlled by a carry output from the next lower bit block.
摘要翻译： 在其中输入数据被分成多个比特块的加法器电路中，每个由多个比特组成并行数据处理的比特块，其中分别设置为逻辑“0”和“1”的进位输入的两个加法器部分 对于LSB块以外的每个块。 每个块中每个部分的和和进位输出通过门电路共同连接，门电路由下一个较低位块的进位输出控制。
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公开(公告)号：US5163127A
公开(公告)日：1992-11-10
申请号：US687772
申请日：1991-04-19
申请人： Nobuyuki Ikumi , Mitsuo Saito , Takeshi Aikawa , Masahide Ohhashi
发明人： Nobuyuki Ikumi , Mitsuo Saito , Takeshi Aikawa , Masahide Ohhashi
CPC分类号： G06T15/87
摘要： A three-dimensional graphic processing apparatus includes n arithmetic ICs (Integrated Circuits) for performing linear interpolation calculations for each scan line of a triangle polygon to obtain intensity values and depth coordinate values of pixels, and two types of n memories for storing the calculation results. The n arithmetic ICs parallelly execute linear interpolation calculations of n different pixels successive on a single scan line of a single triangle polygon in one processing cycle. Each arithmetic IC calculates for each of every n pixels in one processing cycle, and a corresponding one of the memories stores the calculation result.
摘要翻译： 三维图形处理装置包括用于对三角形多边形的每条扫描线进行线性插值计算的n个运算IC（集成电路），以获得像素的强度值和深度坐标值，以及用于存储计算结果的两种类型的n个存储器 。 在一个处理周期中，n个运算IC并行地执行在单个三角形多边形的单个扫描线上连续的n个不同像素的线性插值计算。 每个算术IC在一个处理周期中为每n个像素计算每个运算IC，并且相应的一个存储器存储计算结果。
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公开(公告)号：US4592007A
公开(公告)日：1986-05-27
申请号：US428033
申请日：1982-09-29
申请人： Masahide Ohhashi
发明人： Masahide Ohhashi
CPC分类号： G06F7/5016
摘要： The invention provides a full adder having a logic circuit which has an inverter and a selector circuit, a logic circuit which has an inverter and a selector circuit, and a logic circuit which has a selector circuit and an inverter so as to produce a sum output signal S and a carry output signal C in response to three input signals X, Y and Z.
摘要翻译： 本发明提供了具有逻辑电路的全加器，其具有逆变器和选择器电路，具有逆变器和选择器电路的逻辑电路以及具有选择器电路和反相器以产生和输出的逻辑电路 信号S和进位输出信号C响应于三个输入信号X，Y和Z。
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