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1.发明授权公开(公告)号：US07437697B2
公开(公告)日：2008-10-14
申请号：US11303792
申请日：2005-12-16
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A method for determining criticality probability of an edge of a timing graph of a circuit is described. The method includes forming a directed acyclic timing graph corresponding to a circuit being timed, performing statistical timing of the circuit, for each edge of interest, defining a cutset that divides the timing graph into a plurality of parts, determining an edge slack for each edge in the cutset, computing a statistical maximum of all edge slacks in the cutset, and inferring edge criticality probabilities of each edge from the statistical maximum. A system for determining criticality probability of an edge of a timing graph of a circuit is also described.
摘要翻译： 描述了用于确定电路的时序图的边缘的临界概率的方法。 该方法包括形成对应于正在定时的电路的有向非循环时序图，对于感兴趣的每个边缘执行电路的统计定时，定义将定时图分成多个部分的切片，确定每个边缘的边缘松弛 在切片中，计算切片中所有边缘松弛的统计最大值，并从统计最大值推断每个边缘的边缘关键概率。 还描述了用于确定电路的时序图的边缘的关键概率的系统。
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2.发明申请公开(公告)号：US20070143722A1
公开(公告)日：2007-06-21
申请号：US11303792
申请日：2005-12-16
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A method for determining criticality probability of an edge of a timing graph of a circuit is described. The method includes forming a directed acyclic timing graph corresponding to a circuit being timed, performing statistical timing of the circuit, for each edge of interest, defining a cutset that divides the timing graph into a plurality of parts, determining an edge slack for each edge in the cutset, computing a statistical maximum of all edge slacks in the cutset, and inferring edge criticality probabilities of each edge from the statistical maximum. A system for determining criticality probability of an edge of a timing graph of a circuit is also described.
摘要翻译： 描述了用于确定电路的时序图的边缘的临界概率的方法。 该方法包括形成对应于正在定时的电路的有向非循环时序图，对于感兴趣的每个边缘执行电路的统计定时，定义将定时图分成多个部分的切片，确定每个边缘的边缘松弛 在切片中，计算切片中所有边缘松弛的统计最大值，并从统计最大值推断每个边缘的边缘关键概率。 还描述了用于确定电路的时序图的边缘的关键概率的系统。
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3.发明申请METHOD AND APPARATUS FOR EFFICIENT INCREMENTAL STATISTICAL TIMING ANALYSIS AND OPTIMIZATION 有权有效增量统计时序分析与优化的方法与装置公开(公告)号：US20100088658A1
公开(公告)日：2010-04-08
申请号：US12244512
申请日：2008-10-02
申请人： Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10 , G06F2217/84
摘要： In one embodiment, the invention is a method and apparatus for efficient incremental statistical timing analysis and optimization. One embodiment of a method for determining an incremental extrema of n random variables, given a change to at least one of the n random variables, includes obtaining the n random variables, obtaining a first extrema for the n random variables, where the first extrema is an extrema computed prior to the change to the at least one of the n random variables, removing the at least one of the n random variables to form an (n−1) subset, computing a second extrema for the (n−1) subset in accordance with the first extrema and the at least one of the n random variables, and outputting a new extrema of the n random variables incrementally based on the extrema of the (n−1) subset and the at least one of the n random variables that changed.
摘要翻译： 在一个实施例中，本发明是一种用于有效增量统计时序分析和优化的方法和装置。 给定对n个随机变量中的至少一个的改变的用于确定n个随机变量的增量极值的方法的一个实施例包括获得n个随机变量，获得n个随机变量的第一极值，其中第一极值是 在对所述n个随机变量中的至少一个随机变量进行改变之前计算的极值，去除所述n个随机变量中的所述至少一个以形成（n-1）子集，计算所述（n-1）子集的第二极值 根据第一极值和n个随机变量中的至少一个，并且基于第（n-1）个子集的极值和n个随机变量中的至少一个来递增地输出n个随机变量的新的极值 改变了。
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4.发明授权Method and apparatus for efficient incremental statistical timing analysis and optimization 有权用于高效增量统计时序分析和优化的方法和装置公开(公告)号：US08104005B2
公开(公告)日：2012-01-24
申请号：US12244512
申请日：2008-10-02
申请人： Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10 , G06F2217/84
摘要： In one embodiment, the invention is a method and apparatus for efficient incremental statistical timing analysis and optimization. One embodiment of a method for determining an incremental extrema of n random variables, given a change to at least one of the n random variables, includes obtaining the n random variables, obtaining a first extrema for the n random variables, where the first extrema is an extrema computed prior to the change to the at least one of the n random variables, removing the at least one of the n random variables to form an (n−1) subset, computing a second extrema for the (n−1) subset in accordance with the first extrema and the at least one of the n random variables, and outputting a new extrema of the n random variables incrementally based on the extrema of the (n−1) subset and the at least one of the n random variables that changed.
摘要翻译： 在一个实施例中，本发明是一种用于有效增量统计时序分析和优化的方法和装置。 给定对n个随机变量中的至少一个的改变的用于确定n个随机变量的增量极值的方法的一个实施例包括获得n个随机变量，获得n个随机变量的第一极值，其中第一极值是 在对所述n个随机变量中的至少一个随机变量进行改变之前计算的极值，去除所述n个随机变量中的所述至少一个以形成（n-1）子集，计算所述（n-1）子集的第二极值 根据第一极值和n个随机变量中的至少一个，并且基于第（n-1）个子集的极值和n个随机变量中的至少一个来递增地输出n个随机变量的新的极值 改变了。
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5.发明授权Systems and methods for correlated parameters in statistical static timing analysis 失效统计静态时序分析中相关参数的系统和方法公开(公告)号：US08707233B2
公开(公告)日：2014-04-22
申请号：US13190083
申请日：2011-07-25
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
CPC分类号： G06F17/5031 , G06F17/5081
摘要： Systems and methods for accommodating correlated parameters in SSTA are provided. The method includes determining a correlation between at least two parameters. The method further includes calculating a new parameter or a new parameter set based on the correlation between the at least two parameters. The method further includes performing the SSTA such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes projecting slack using the correlation between the at least two parameters and using a processor.
摘要翻译： 提供了适应SSTA相关参数的系统和方法。 该方法包括确定至少两个参数之间的相关性。 该方法还包括基于至少两个参数之间的相关性计算新参数或新参数集。 该方法还包括执行SSTA，使得新参数或新参数集传播到SSTA中。 该方法还包括使用至少两个参数之间的相关性并使用处理器来投影松弛。
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6.发明授权System and method for performing static timing analysis in the presence of correlations between asserted arrival times 失效在断言到达时间之间存在相关性的情况下执行静态时序分析的系统和方法公开(公告)号：US08689158B2
公开(公告)日：2014-04-01
申请号：US12944059
申请日：2010-11-11
申请人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Jeffrey G. Hemmett , Peihua Qi , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Kerim Kalafala , Jennifer E. Basile , David J. Hathaway , Jeffrey G. Hemmett , Peihua Qi , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F2217/84
摘要： A method of applying common path credit in a static timing analysis in the presence of correlations between asserted arrival times, comprising the steps of using a computer, identifying one or more pairs of asserted arrival times for which one or more correlations exist; propagating to each of the one or more pairs of asserted arrival times a timing value dependent on the one or more correlations; and performing a subsequent common path pessimism removal analysis for at least one test during which a timing value dependent on the one or more correlations between asserted arrival times is used to compute an adjusted test slack.
摘要翻译： 一种在断言到达时间之间的相关性存在的静态时序分析中应用公共路径信用的方法，包括以下步骤：使用计算机识别存在一个或多个相关性的一个或多个断言到达时间对; 将所述一个或多个断言到达时间对中的每一个传播到取决于所述一个或多个相关性的定时值; 以及对至少一个测试执行随后的公共路径悲观消除分析，在该测试期间，使用取决于所述到达时间之间的一个或多个相关性的定时值来计算经调整的测试松弛。
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7.发明申请METHOD, SYSTEM AND PROGRAM STORAGE DEVICE FOR PERFORMING A PARAMETERIZED STATISTICAL STATIC TIMING ANALYSIS (SSTA) OF AN INTEGRATED CIRCUIT TAKING INTO ACCOUNT SETUP AND HOLD MARGIN INTERDEPENDENCE 失效方法，系统和程序存储设备，用于执行进入帐户设置的集成电路的参数统计静态时序分析（SSTA）并保持标准间隔公开(公告)号：US20130104092A1
公开(公告)日：2013-04-25
申请号：US13279373
申请日：2011-10-24
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladimir Zolotov
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： In embodiments of a statistical static timing analysis (SSTA) method, system and program storage device, the interdependence between the setup time and hold time margins of a circuit block (e.g., a latch, flip-flop, etc., which requires the checking of setup and hold timing constraints) is determined, taking into account possible variations in multiple parameters (e.g., using a variation-aware characterizing technique). A parameterized statistical static timing analysis (SSTA) of a circuit incorporating the circuit block is performed in order to determine, in statistical parameterized form, setup and hold times for the circuit block. Based on the interdependence between the setup and hold time margins, setup and hold time constraints can be determined in statistical parameterized form. Finally, the setup and hold times determined during the SSTA can be checked against the setup and hold time constraints to determine, if the time constraints are violated or not and to what degree.
摘要翻译： 在统计静态时序分析（SSTA）方法，系统和程序存储装置的实施例中，需要检查的电路块（例如，锁存器，触发器等）的建立时间和保持时间裕度之间的相互依赖关系 确定设置和保持时序约束），同时考虑到多个参数的可能变化（例如，使用变异感知特性技术）。 执行结合电路块的电路的参数化统计静态时序分析（SSTA），以便以统计参数化形式确定电路块的建立和保持时间。 基于设置和保持时间间隔之间的相互依赖性，可以以统计参数化形式确定建立和保持时间约束。 最后，可以根据建立和保持时间约束来检查SSTA期间确定的建立和保持时间，以确定是否违反时间限制，以及在何种程度上。
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公开(公告)号：US20090241078A1
公开(公告)日：2009-09-24
申请号：US12053887
申请日：2008-03-24
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method is provided for memory conservation in statistical static timing analysis. A timing graph is created with a timing run in a statistical static timing analysis program. A plurality of nodes in the timing graph that are candidates for a partial store and constraint points are identified. Timing data is persistently stored at constraint points. The persistent timing data is retrieved from the constraint points and used to calculate intermediate timing data at the plurality of nodes during timing analysis.
摘要翻译： 在统计静态时序分析中提供了一种用于存储器保存的方法。 在统计静态时序分析程序中使用时序运行创建时序图。 识别作为部分存储和约束点的候选的定时图中的多个节点。 定时数据被持久存储在约束点。 从约束点检索持续定时数据，并用于在定时分析期间计算多个节点处的中间定时数据。
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9.发明申请METHOD, SYSTEM, AND PROGRAM PRODUCT FOR ACCOMMODATING SPATIALLY-CORRELATED VARIATION IN A PROCESS PARAMETER 失效方法，系统和程序产品，适用于过程参数中的空间相关变化公开(公告)号：US20070118331A1
公开(公告)日：2007-05-24
申请号：US11272234
申请日：2005-11-10
IPC分类号： G06F17/18
CPC分类号： G06F17/5031
摘要： The invention provides a method, system, and program product for accommodating spatially-correlated variation in a process parameter during statistical timing of a circuit. In one embodiment, the method includes dividing an area of the circuit into a plurality of grid cells; associating an independent random variable with each of the plurality of grid cells; and expressing at least one spatially-correlated parameter of a first grid cell as a function of the random variables associated with the first grid cell and at least one neighboring grid cell.
摘要翻译： 本发明提供一种用于在电路的统计定时期间适应处理参数的空间相关变化的方法，系统和程序产品。 在一个实施例中，该方法包括将电路的区域划分成多个网格单元; 将独立随机变量与所述多个网格单元中的每一个相关联; 以及将与第一网格单元和至少一个相邻网格单元相关联的随机变量的函数表达为第一网格单元的至少一个空间相关参数。
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10.发明授权Performing statistical timing analysis with non-separable statistical and deterministic variations 失效用不可分的统计和确定性变化进行统计时序分析公开(公告)号：US08418107B2
公开(公告)日：2013-04-09
申请号：US12943541
申请日：2010-11-10
申请人： Jeffrey G Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Jeffrey G Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
CPC分类号： G06F17/504 , G06F2217/10 , G06F2217/84
摘要： In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and stews at the corresponding corner.
摘要翻译： 在一个实施例中，本发明是用于以不可分的统计和确定性变化执行统计时序分析的方法和装置。 用于执行集成电路芯片的定时分析的方法的一个实施例包括计算芯片栅极和导线的延迟和压摆，其中所述延迟和压摆取决于至少一个确定性和基于角的第一工艺参数，以及第二工艺参数 其与第一过程参数是统计的且不可分离的，并且使用定时数量执行单个定时运行，其中单个定时运行产生到达时间，所需的到达时间和定时偏移在输出，锁存器和电路节点 集成电路芯片。 计算的到达时间，所需的到达时间和时间休息可以被计算为确定性变化的角落值，以便获得相应角落处的延迟和炖菜的统计模型。
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