公开(公告)号：US20130283223A1

公开(公告)日：2013-10-24

申请号：US13454795

申请日：2012-04-24

申请人： Bhavna Agrawal ,  David S. Kung ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： Bhavna Agrawal ,  David S. Kung ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G01R31/31725 ,  G06F2217/10 ,  G06F2217/84

摘要： In one embodiment, the invention is a method and apparatus for variation enabling statistical testing using deterministic multi-corner timing analysis. One embodiment of a method for obtaining statistical timing data for an integrated circuit chip includes obtaining deterministic multi-corner timing data for the integrated circuit chip and constructing the statistical timing data from the deterministic multi-corner timing data.

摘要翻译： 在一个实施例中，本发明是用于使用确定性多角时间分析进行统计测试的变化的方法和装置。 用于获得用于集成电路芯片的统计定时数据的方法的一个实施例包括获得用于集成电路芯片的确定性多角定时数据并从确定性多角定时数据构建统计定时数据。

公开(公告)号：US08510696B2

公开(公告)日：2013-08-13

申请号：US13422637

申请日：2012-03-16

申请人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir P. Zolotov

发明人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir P. Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/50

摘要： Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity.

摘要翻译： 公布统计相关数量排序的解决方案。 在一个方面，一种方法包括对集成电路中的多个路径进行定时以确定与多个路径中的每一条相关联的一组定时量; 确定所述一组定时数量中最关键的定时数量; 形成用于在所述一组定时量中排序多个定时量的分层定时量排列; 从所述定时量集合中去除最关键的定时数量，并将最关键的定时数量置于分层定时数量排列的最上层可用层; 并且重复确定，形成和去除不包括去除的最关键定时量的一组定时量。

公开(公告)号：US20130125076A1

公开(公告)日：2013-05-16

申请号：US13294220

申请日：2011-11-11

申请人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Jinjun Xiong

发明人： Jeanne P. Bickford ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Jinjun Xiong

IPC分类号： G06F17/50

CPC分类号： G01R31/3016 ,  G01R31/31725

摘要： A method and system for dispositioning integrated circuit chips. The method includes performing a performance path test on an integrated circuit chip having one or more clock domains, the performance path test based on applying test patterns to selected sensitizable data paths of the integrated circuit chip at different clock frequencies; and dispositioning the integrated circuit chip based on results of the performance path test.

摘要翻译： 一种配置集成电路芯片的方法和系统。 该方法包括对具有一个或多个时钟域的集成电路芯片执行性能路径测试，该性能路径测试基于将测试图案应用于集成电路芯片的不同时钟频率的选择的可敏化数据路径; 并且基于性能路径测试的结果来布置集成电路芯片。

公开(公告)号：US20130014075A1

公开(公告)日：2013-01-10

申请号：US13617749

申请日：2012-09-14

申请人： Peter Anton Habitz ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： Peter Anton Habitz ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G01R31/31718 ,  G01R31/31725 ,  G06F17/5031 ,  G06F2217/84

摘要： A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure.

摘要翻译： 集成电路（IC）配置的方法包括至少部分地基于给定IC设计的统计定时来确定一个或多个处置标准的步骤; 以及至少部分地基于至少一个测试结构的一个或多个测量来确定根据给定IC设计的给定IC是否满足所述一个或多个处置标准。

公开(公告)号：US20120191401A1

公开(公告)日：2012-07-26

申请号：US13439188

申请日：2012-04-04

申请人： CHANDRAMOULI VISWESWARIAH ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： CHANDRAMOULI VISWESWARIAH ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G06F19/00

CPC分类号： G01R31/318328 ,  G01R31/318342

摘要： In one embodiment, the invention is a method and apparatus generating test patterns for use in at-speed testing. One embodiment of a method for use by a general purpose computing device that is configured to generate a set of test patterns with which to test an integrated circuit chip includes receiving, by an input device of the general purpose computing device, statistical timing information relating to the integrated circuit chip and a logic circuit of the integrated circuit chip and generating, by a processor of the general purpose computing device, the set of test patterns in accordance with the statistical timing information while simultaneously selecting a set of paths on which to test the set of test patterns.

摘要翻译： 在一个实施例中，本发明是产生用于在速测试中的测试图案的方法和装置。 由通用计算设备使用的方法的一个实施例被配置为生成用于测试集成电路芯片的一组测试图案，包括由通用计算设备的输入设备接收与 所述集成电路芯片和所述集成电路芯片的逻辑电路，并且由所述通用计算设备的处理器根据所述统计定时信息生成所述一组测试图案，同时选择一组在其上测试的路径 一套测试模式。

公开(公告)号：US20120124535A1

公开(公告)日：2012-05-17

申请号：US12946950

申请日：2010-11-16

申请人： Jinjun Xiong ,  Vladimir Zolotov

发明人： Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G01R31/31718

摘要： At least one target metric is identified for an integrated circuit chip design for which manufacturing chip testing is to be optimized. At least one surrogate metric is also identified for the integrated circuit chip design for which manufacturing chip testing is to be optimized. A relationship between the at least one target metric and the at least one surrogate metric is modeled using a general joint probability density function. A chip disposition criterion is determined based on the general joint probability density function. The chip disposition criterion determines, for a given physical chip putatively manufactured in accordance with the design, based on the at least one surrogate metric for the given physical chip, whether the given physical chip is to be accepted or discarded during the manufacturing chip testing.

摘要翻译： 针对要优化制造芯片测试的集成电路芯片设计识别至少一个目标度量。 还针对要优化制造芯片测试的集成电路芯片设计识别至少一个替代度量。 使用一般联合概率密度函数来建模所述至少一个目标度量和所述至少一个代理度量之间的关系。 基于通用联合概率密度函数确定芯片配置准则。 芯片配置标准对于根据设计推定制造的给定物理芯片，基于给定物理芯片的至少一个替代度量来确定在制造芯片测试期间是否接受或丢弃给定的物理芯片。

公开(公告)号：US08176462B2

公开(公告)日：2012-05-08

申请号：US12464025

申请日：2009-05-11

申请人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G06F11/22 ,  G06F17/50

CPC分类号： G01R31/318328 ,  G01R31/318342

摘要： In one embodiment, the invention is a method and apparatus generating test patterns for use in at-speed testing. One embodiment of a method for use by a general purpose computing device that is configured to generate a set of test patterns with which to test an integrated circuit chip includes receiving, by an input device of the general purpose computing device, statistical timing information relating to the integrated circuit chip and a logic circuit of the integrated circuit chip and generating, by a processor of the general purpose computing device, the set of test patterns in accordance with the statistical timing information while simultaneously selecting a set of paths on which to test the set of test patterns.

摘要翻译： 在一个实施例中，本发明是产生用于在速测试中的测试图案的方法和装置。 由通用计算设备使用的方法的一个实施例被配置为生成用于测试集成电路芯片的一组测试图案，包括由通用计算设备的输入设备接收与 所述集成电路芯片和所述集成电路芯片的逻辑电路，并且由所述通用计算设备的处理器根据所述统计定时信息生成所述一组测试图案，同时选择一组在其上测试的路径 一套测试模式。

公开(公告)号：US20100162064A1

公开(公告)日：2010-06-24

申请号：US12340072

申请日：2008-12-19

申请人： Yiyu Shi ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： Yiyu Shi ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/2882

摘要： In one embodiment, the invention is a method and apparatus covering a multilayer process space during at-speed testing. One embodiment of a method for selecting a set of paths with which to test a process space includes determining a number N of paths to be included in the set of paths such that at least number M of paths in N for which testing of the process space will fail, computing a metric that substantially ensures that the set of paths satisfies the requirements of N and M, and outputting the metric for use in selecting the set of paths.

摘要翻译： 在一个实施例中，本发明是在高速测试期间覆盖多层工艺空间的方法和装置。 用于选择用于测试处理空间的一组路径的方法的一个实施例包括确定要包括在路径集合中的路径数量N，使得至少数目M的路径在其中用于对进程空间进行测试 将会失败，计算基本上确保路径组满足N和M要求并输出用于选择路径集合的度量的度量。

公开(公告)号：US20100088658A1

公开(公告)日：2010-04-08

申请号：US12244512

申请日：2008-10-02

申请人： Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/10 ,  G06F2217/84

摘要： In one embodiment, the invention is a method and apparatus for efficient incremental statistical timing analysis and optimization. One embodiment of a method for determining an incremental extrema of n random variables, given a change to at least one of the n random variables, includes obtaining the n random variables, obtaining a first extrema for the n random variables, where the first extrema is an extrema computed prior to the change to the at least one of the n random variables, removing the at least one of the n random variables to form an (n−1) subset, computing a second extrema for the (n−1) subset in accordance with the first extrema and the at least one of the n random variables, and outputting a new extrema of the n random variables incrementally based on the extrema of the (n−1) subset and the at least one of the n random variables that changed.

摘要翻译： 在一个实施例中，本发明是一种用于有效增量统计时序分析和优化的方法和装置。 给定对n个随机变量中的至少一个的改变的用于确定n个随机变量的增量极值的方法的一个实施例包括获得n个随机变量，获得n个随机变量的第一极值，其中第一极值是 在对所述n个随机变量中的至少一个随机变量进行改变之前计算的极值，去除所述n个随机变量中的所述至少一个以形成（n-1）子集，计算所述（n-1）子集的第二极值 根据第一极值和n个随机变量中的至少一个，并且基于第（n-1）个子集的极值和n个随机变量中的至少一个来递增地输出n个随机变量的新的极值 改变了。

公开(公告)号：US07480880B2

公开(公告)日：2009-01-20

申请号：US11358622

申请日：2006-02-21

申请人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

发明人： Chandramouli Visweswariah ,  Jinjun Xiong ,  Vladimir Zolotov

IPC分类号： G06F17/50 ,  G06F17/10

CPC分类号： G06F17/509 ,  G06F17/5031 ,  G06F17/504 ,  G06F2217/10 ,  G06F2217/12 ,  Y02P90/265

摘要： The invention provides a method, system, and program product for determining a gradient of a parametric yield of an integrated circuit with respect to parameters of a delay of an edge of a timing graph of the circuit. A first aspect of the invention provides a method for determining a gradient of a parametric yield of an integrated circuit with respect to parameters of a delay of an edge of a timing graph of the circuit, the method comprising: conducting a statistical timing analysis; expressing a statistical circuit delay in terms of a delay of the edge; and computing a gradient of the statistical circuit delay with respect to parameters of the delay of the edge.

摘要翻译： 本发明提供了一种方法，系统和程序产品，用于相对于电路的时序图的边沿的延迟的参数来确定集成电路的参数收益率的梯度。 本发明的第一方面提供了一种用于根据电路的时序图的边沿的延迟的参数来确定集成电路的参数收益率的梯度的方法，所述方法包括：执行统计时序分析; 根据边缘的延迟表示统计电路延迟; 以及计算相对于边缘的延迟的参数的统计电路延迟的梯度。