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1.发明授权公开(公告)号：US07702944B2
公开(公告)日：2010-04-20
申请号：US12352108
申请日：2009-01-12
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/324 , Y02D10/126
摘要： The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element.
摘要翻译： 本发明提供了在改变时钟频率时减少电路中的电流尖峰。 第一个频率被应用到时钟分配网络。 选择最终频率。 第一个频率通过时钟分配网络应用于逻辑元件。 保持信号被施加到逻辑元件。 时钟分配网络的时钟速率从第一个频率改变到最后的频率。 保持信号未应用于逻辑元件。
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公开(公告)号：US20090119552A1
公开(公告)日：2009-05-07
申请号：US12352108
申请日：2009-01-12
IPC分类号： G06F11/00
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/324 , Y02D10/126
摘要： The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element.
摘要翻译： 本发明提供了在改变时钟频率时减少电路中的电流尖峰。 第一个频率被应用到时钟分配网络。 选择最终频率。 第一个频率通过时钟分配网络应用于逻辑元件。 保持信号被施加到逻辑元件。 时钟分配网络的时钟速率从第一个频率改变到最后的频率。 保持信号未应用于逻辑元件。
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3.发明授权公开(公告)号：US07516350B2
公开(公告)日：2009-04-07
申请号：US10937689
申请日：2004-09-09
CPC分类号： G06F1/3203 , G06F1/08 , G06F1/324 , Y02D10/126
摘要： The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element.
摘要翻译： 本发明提供了在改变时钟频率时减少电路中的电流尖峰。 第一个频率被应用到时钟分配网络。 选择最终频率。 第一个频率通过时钟分配网络应用于逻辑元件。 保持信号被施加到逻辑元件。 时钟分配网络的时钟速率从第一个频率改变到最后的频率。 保持信号未应用于逻辑元件。
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4.发明授权Method to gate off PLLS in a deep power saving state without separate clock distribution for power management logic 有权在功率管理逻辑没有单独的时钟分配的情况下，在深省电状态下关闭PLLS的方法公开(公告)号：US07656237B2
公开(公告)日：2010-02-02
申请号：US11002559
申请日：2004-12-02
IPC分类号： H03L7/095
CPC分类号： G06F1/04 , G06F1/3203 , G06F1/3237 , H03L7/06 , Y02D10/126 , Y02D10/128 , Y10S331/02
摘要： An apparatus, a method, and a computer program are provided to gate a Phased Locked Loop (PLL). In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Gating the PLLs, however, has been difficult because of the usual requirement for a separate clock for control logic and because the PLL requires timed to reacquire phase/frequency lock. Therefore, lock detection logic can be employed to allow the PLL to reacquire phase/frequency lock. Additionally, signals from external devices and the processor can be employed to gate the PLL and allow the processor to be awakened without a need for a separate clock.
摘要翻译： 提供了一种设备，方法和计算机程序来对相位锁定环路（PLL）进行门控。 在微处理器中，时钟分配系统可以占用大量的功耗。 然而，门控门限是困难的，因为控制逻辑需要单独的时钟，因为PLL需要定时重新获取相位/频率锁定。 因此，可以采用锁定检测逻辑来允许PLL重新获取相位/频率锁定。 此外，可以采用来自外部设备和处理器的信号来门控PLL，并且允许处理器被唤醒而无需单独的时钟。
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5.发明授权Deep power saving by disabling clock distribution without separate clock distribution for power management logic 有权通过禁用时钟分配，无需电源管理逻辑的单独时钟分配即可实现深度省电公开(公告)号：US07284138B2
公开(公告)日：2007-10-16
申请号：US11002551
申请日：2004-12-02
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128
摘要： An apparatus, a method, and a computer program are provided to disable clock distribution. In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Disabling the clock distribution system, however, has been difficult because of the usual requirement for a separate clock for control logic. Therefore, combinational logic can be employed to disrupt the clock distribution and allow a processor to be awakened without a need for a separate clock.
摘要翻译： 提供了一种装置，方法和计算机程序来禁止时钟分配。 在微处理器中，时钟分配系统可以占用大量的功耗。 然而，禁用时钟分配系统是困难的，因为通常需要用于控制逻辑的单独时钟。 因此，可以采用组合逻辑来中断时钟分配，并且允许处理器被唤醒而不需要单独的时钟。
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6.发明申请公开(公告)号：US20090121747A1
公开(公告)日：2009-05-14
申请号：US11938347
申请日：2007-11-12
申请人： Sang Hoo Dhong , Peter Harm Hofstee , Mack Wayne Riley , James Douglas Warnock , Stephen Douglas Weitzel
发明人： Sang Hoo Dhong , Peter Harm Hofstee , Mack Wayne Riley , James Douglas Warnock , Stephen Douglas Weitzel
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K19/0008
摘要： A system and method for maintaining circuit delay characteristics during power management mode. The method for maintaining circuit delay characteristics during power management mode continually toggles the clock distribution circuits at a frequency sufficiently low that it does not significantly impact chip power dissipation. The clock frequency used to toggle the clock distribution circuits is high enough to minimize the asymmetrical stress on the clock buffer transistors so that both P and N device characteristics equally change over time.
摘要翻译： 一种用于在电源管理模式下维持电路延迟特性的系统和方法。 用于在电源管理模式期间维持电路延迟特性的方法连续地将时钟分配电路切换到足够低的频率，使其不会显着影响芯片功率耗散。 用于切换时钟分配电路的时钟频率足够高以最小化时钟缓冲晶体管上的不对称应力，以便P和N器件特性随时间均匀变化。
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7.发明申请Circuit to Reduce Transient Current Swings During Mode Transitions of High Frequency/High Power Chips 有权在高频/高功率芯片模式转换期间减少瞬态电流摆幅的电路公开(公告)号：US20080272820A1
公开(公告)日：2008-11-06
申请号：US12132871
申请日：2008-06-04
IPC分类号： H03K3/00
CPC分类号： H03K23/662 , G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.
摘要翻译： 提供了一种方法，装置和计算机程序以减少模式转换期间的瞬态电流摆动。 传统上，芯片上的瞬态电源电压波动占大部分电源。 串联电感和电阻的数量通常最小化，同时在电源电压和地之间增加大的去耦电容。 然而，不能实现串联电感和电阻的降低的情况。 因此，为了帮助控制瞬态电流摆动，以受控的方式执行时钟频率的降低。
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8.发明申请System and Method for Advanced Logic Built-in Self Test with Selection of Scan Channels 失效用于高级逻辑内置自检的系统和方法，可选择扫描通道公开(公告)号：US20080052579A1
公开(公告)日：2008-02-28
申请号：US11463904
申请日：2006-08-11
申请人： Mack Wayne Riley , Michael Fan Wang
发明人： Mack Wayne Riley , Michael Fan Wang
IPC分类号： G01R31/28
CPC分类号： G01R31/318575
摘要： A system and method for advanced logic built-in self test with selection of scan channels is present. An LBIST controller loads scan patterns into a device's scan channels through sequential or interleaved loading techniques in order to minimize instantaneous power requirements. During interleave loading, the LBIST controller loads a scan bit into a first scan chain, then into a second scan chain, etc. until one bit is loaded into each scan chain. The LBIST controller then returns to load another scan bit into the first scan channel, then the second scan channel, etc. During sequential loading, the LBIST controller loads an entire scan pattern into a first scan chain (one bit per clock cycle). Once the first scan pattern is loaded, the LBIST controller proceeds to load subsequent scan patterns into corresponding scan chains on a one bit per scan channel per clock cycle basis.
摘要翻译： 存在具有选择扫描通道的高级逻辑内置自检的系统和方法。 LBIST控制器通过顺序或交错加载技术将扫描图案加载到设备的扫描通道中，以最小化瞬时功率需求。 在交错加载期间，LBIST控制器将扫描位加载到第一个扫描链中，然后加载到第二个扫描链等中，直到一个位加载到每个扫描链中。 LBIST控制器然后返回将另一个扫描位加载到第一个扫描通道，然后是第二个扫描通道等。在连续加载期间，LBIST控制器将整个扫描模式加载到第一个扫描链（每个时钟周期一个位）。 一旦加载了第一个扫描模式，LBIST控制器就会按照每个时钟周期的每个扫描通道一个位的速度将后续扫描模式加载到相应的扫描链中。
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9.发明授权Circuit to reduce power supply fluctuations in high frequency/high power circuits 有权降低高频/高功率电路电源波动的电路公开(公告)号：US07809974B2
公开(公告)日：2010-10-05
申请号：US12014830
申请日：2008-01-16
IPC分类号： H04L25/00
CPC分类号： G06F1/26
摘要： A circuit for transitioning clocking speeds, or frequencies, is provided. With this circuit, a clocking circuit providing a first clock signal at a first clock frequency is coupled to a counter. A comparator and a first divider are coupled to an output of the counter. The first divider outputs a second clock signal at a second clock frequency. A second divider is interposed between the clocking circuit and the counter. A processor is coupled to an output of the first divider.
摘要翻译： 提供了用于转换时钟速度或频率的电路。 利用该电路，以第一时钟频率提供第一时钟信号的时钟电路被耦合到计数器。 比较器和第一分频器耦合到计数器的输出端。 第一分频器以第二时钟频率输出第二时钟信号。 在时钟电路和计数器之间插入第二分频器。 处理器耦合到第一分频器的输出端。
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10.发明授权Method to reduce transient current swings during mode transitions of high frequency/high power chips 失效在高频/高功率芯片的模式转换期间减少瞬态电流摆幅的方法公开(公告)号：US07430264B2
公开(公告)日：2008-09-30
申请号：US10981154
申请日：2004-11-04
CPC分类号： H03K23/662 , G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.
摘要翻译： 提供了一种方法，装置和计算机程序以减少模式转换期间的瞬态电流摆动。 传统上，芯片上的瞬态电源电压波动占大部分电源。 串联电感和电阻的数量通常最小化，同时在电源电压和地之间增加大的去耦电容。 然而，不能实现串联电感和电阻的降低的情况。 因此，为了帮助控制瞬态电流摆动，以受控的方式执行时钟频率的降低。
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