公开(公告)号：US09880846B2

公开(公告)日：2018-01-30

申请号：US13444673

申请日：2012-04-11

申请人： Nathan Tuck ,  Ross Segelken

发明人： Nathan Tuck ,  Ross Segelken

IPC分类号： G06F9/455 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3808 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/4552

摘要： In one embodiment, a micro-processing system includes a hardware structure disposed on a processor core. The hardware structure includes a plurality of entries, each of which are associated with portion of code and a translation of that code which can be executed to achieve substantially equivalent functionality. The hardware structure includes a redirection array that enables, when referenced, execution to be redirected from a portion of code to its counterpart translation. The entries enabling such redirection are maintained within or evicted from the hardware structure based on usage information for the entries.

公开(公告)号：US10146545B2

公开(公告)日：2018-12-04

申请号：US13419323

申请日：2012-03-13

申请人： Ross Segelken ,  Alex Klaiber ,  Nathan Tuck ,  David Dunn

发明人： Ross Segelken ,  Alex Klaiber ,  Nathan Tuck ,  David Dunn

IPC分类号： G06F12/10 ,  G06F9/30 ,  G06F12/1018 ,  G06F12/0862 ,  G06F9/38

摘要： Embodiments related to fetching instructions and alternate versions achieving the same functionality as the instructions from an instruction cache included in a microprocessor are provided. In one example, a method is provided, comprising, at an example microprocessor, fetching an instruction from an instruction cache. The example method also includes hashing an address for the instruction to determine whether an alternate version of the instruction which achieves the same functionality as the instruction exists. The example method further includes, if hashing results in a determination that such an alternate version exists, aborting fetching of the instruction and retrieving and executing the alternate version.

公开(公告)号：US20130246709A1

公开(公告)日：2013-09-19

申请号：US13419323

申请日：2012-03-13

申请人： Ross Segelken ,  Alex Klaiber ,  Nathan Tuck ,  David Dunn

发明人： Ross Segelken ,  Alex Klaiber ,  Nathan Tuck ,  David Dunn

IPC分类号： G06F12/08

CPC分类号： G06F9/30181 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3802 ,  G06F12/0862 ,  G06F12/1018

摘要： Embodiments related to fetching instructions and alternate versions achieving the same functionality as the instructions from an instruction cache included in a microprocessor are provided. In one example, a method is provided, comprising, at an example microprocessor, fetching an instruction from an instruction cache. The example method also includes hashing an address for the instruction to determine whether an alternate version of the instruction which achieves the same functionality as the instruction exists. The example method further includes, if hashing results in a determination that such an alternate version exists, aborting fetching of the instruction and retrieving and executing the alternate version.

摘要翻译： 提供了与从微处理器中包括的指令高速缓存的指令获取相同功能的取指令和替代版本的实施例。 在一个示例中，提供了一种方法，其包括以示例性微处理器从指令高速缓存取出指令。 示例性方法还包括对用于指令的地址进行散列以确定实现与指令相同功能的指令的替代版本是否存在。 该示例方法还包括，如果散列导致存在这样的替代版本的确定，则中止提取指令并检索和执行备用版本。

公开(公告)号：US20130275684A1

公开(公告)日：2013-10-17

申请号：US13444673

申请日：2012-04-11

申请人： Nathan Tuck ,  Ross Segelken

发明人： Nathan Tuck ,  Ross Segelken

IPC分类号： G06F12/08

CPC分类号： G06F9/3808 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/4552

摘要： In one embodiment, a micro-processing system includes a hardware structure disposed on a processor core. The hardware structure includes a plurality of entries, each of which are associated with portion of code and a translation of that code which can be executed to achieve substantially equivalent functionality. The hardware structure includes a redirection array that enables, when referenced, execution to be redirected from a portion of code to its counterpart translation. The entries enabling such redirection are maintained within or evicted from the hardware structure based on usage information for the entries.

摘要翻译： 在一个实施例中，微处理系统包括设置在处理器核心上的硬件结构。 硬件结构包括多个条目，每个条目与代码的一部分相关联，并且该代码的转换可以被执行以实现基本相同的功能。 硬件结构包括重定向阵列，当被引用时，执行被重定向到一部分代码到其对应的转换。 基于条目的使用信息，启用这种重定向的条目被保持在硬件结构内或从硬件结构中驱逐。

公开(公告)号：US09396117B2

公开(公告)日：2016-07-19

申请号：US13346536

申请日：2012-01-09

申请人： Aneesh Aggarwal ,  Ross Segelken ,  Kevin Koschoreck

发明人： Aneesh Aggarwal ,  Ross Segelken ,  Kevin Koschoreck

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/08

CPC分类号： G06F12/0864 ,  G06F12/0875 ,  G06F2212/1028 ,  Y02D10/13

摘要： In one embodiment, a method for controlling an instruction cache including a least-recently-used bits array, a tag array, and a data array, includes looking up, in the least-recently-used bits array, least-recently-used bits for each of a plurality of cacheline sets in the instruction cache, determining a most-recently-used way in a designated cacheline set of the plurality of cacheline sets based on the least-recently-used bits for the designated cacheline, looking up, in the tag array, tags for one or more ways in the designated cacheline set, looking up, in the data array, data stored in the most-recently-used way in the designated cacheline set, and if there is a cache hit in the most-recently-used way, retrieving the data stored in the most-recently-used way from the data array.

摘要翻译： 在一个实施例中，一种用于控制包括最近最少使用的位阵列，标签阵列和数据阵列的指令高速缓存的方法包括在最近最少使用的位阵列中查找最近最少使用的位 对于指令高速缓存中的多个高速缓存行集合中的每一个，基于指定的高速缓存行的最近最少使用的比特来确定在多个高速缓存行集合的指定的高速缓存行集合中的最近使用的方式，查找 标签数组，在指定的高速缓存行集中的一种或多种方式的标签，在数据数组中查找，以指定的高速缓存行集合中最近使用的方式存储的数据，以及如果最多存在高速缓存命中 以最常用的方式，从数据数组中检索以最近使用的方式存储的数据。

公开(公告)号：US20130297911A1

公开(公告)日：2013-11-07

申请号：US13463627

申请日：2012-05-03

申请人： Guillermo J. Rozas ,  Paul Serris ,  Brad Hoyt ,  Sridharan Ramakrishnan ,  Hens Vanderschoot ,  Ross Segelken ,  Darrell Boggs ,  Magnus Ekman

发明人： Guillermo J. Rozas ,  Paul Serris ,  Brad Hoyt ,  Sridharan Ramakrishnan ,  Hens Vanderschoot ,  Ross Segelken ,  Darrell Boggs ,  Magnus Ekman

IPC分类号： G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/3814 ,  G06F9/3863

摘要： Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic, and scheduler logic for scheduling the retrieved instruction for execution. The example scheduler logic includes a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.

摘要翻译： 在提供微控制器重新进入特定执行位置之后，重新分派从缓冲器重新执行的指令的实施例。 在一个示例中，提供微处理器。 示例微处理器包括提取逻辑，用于执行由提取逻辑提供的检索指令的一个或多个执行机制，以及用于调度所检索的指令以执行的调度器逻辑。 示例调度器逻辑包括用于存储检索到的指令和一个或多个附加指令的缓冲器，调度器逻辑被配置为在微控制器在经过前导头之后的特定执行位置重新进入时从缓冲器重新发送指令 以前已经分配到其中一个执行机制。

公开(公告)号：US20130290676A1

公开(公告)日：2013-10-31

申请号：US13458513

申请日：2012-04-27

申请人： Aneesh Aggarwal ,  Ross Segelken ,  Paul Wasson

发明人： Aneesh Aggarwal ,  Ross Segelken ,  Paul Wasson

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F1/3243 ,  G06F9/30058 ,  Y02D10/152

摘要： In one embodiment, a microprocessor is provided. The microprocessor includes a branch prediction unit. The branch prediction unit is configured to track the presence of branches in instruction data that is fetched from an instruction memory after a redirection at a target of a predicted taken branch. The branch prediction unit is selectively powered up from a powered-down state when the fetched instruction data includes a branch instruction and is maintained in the powered-down state when the fetched instruction data does not include an instruction branch in order to reduce power consumption of the microprocessor during instruction fetch operations.

摘要翻译： 在一个实施例中，提供微处理器。 微处理器包括分支预测单元。 分支预测单元被配置为跟踪在预测的分支的目标上的重定向之后从指令存储器取出的指令数据中的分支的存在。 当获取的指令数据包括分支指令时，分支预测单元从掉电状态选择性地加电，并且当所提取的指令数据不包括指令分支时，分支预测单元被维持在掉电状态，以便降低功耗 指令提取操作期间的微处理器。

公开(公告)号：US20130311752A1

公开(公告)日：2013-11-21

申请号：US13475755

申请日：2012-05-18

申请人： Rupert Brauch ,  Madhu Swarna ,  Ross Segelken ,  David Dunn ,  Ben Hertzberg

发明人： Rupert Brauch ,  Madhu Swarna ,  Ross Segelken ,  David Dunn ,  Ben Hertzberg

IPC分类号： G06F9/30

CPC分类号： G06F9/45516 ,  G06F9/30174

摘要： A processing system comprising a microprocessor core and a translator. Within the microprocessor core is arranged a hardware decoder configured to selectively decode instructions for execution in the microprocessor core, and, a logic structure configured to track usage of the hardware decoder. The translator is operatively coupled to the logic structure and configured to selectively translate the instructions for execution in the microprocessor core, based on the usage of the hardware decoder as determined by the logic structure.

摘要翻译： 一种包括微处理器核心和转换器的处理系统。 在微处理器核心内布置有硬件解码器，其被配置为选择性地解码用于在微处理器核心中执行的指令，以及被配置为跟踪硬件解码器的使用的逻辑结构。 翻译器可操作地耦合到逻辑结构并且被配置为基于由逻辑结构确定的硬件解码器的使用来选择性地转换用于在微处理器核心中执行的指令。

公开(公告)号：US20130179640A1

公开(公告)日：2013-07-11

申请号：US13346536

申请日：2012-01-09

申请人： Aneesh Aggarwal ,  Ross Segelken ,  Kevin Koschoreck

发明人： Aneesh Aggarwal ,  Ross Segelken ,  Kevin Koschoreck

IPC分类号： G06F12/12

CPC分类号： G06F12/0864 ,  G06F12/0875 ,  G06F2212/1028 ,  Y02D10/13

摘要： In one embodiment, a method for controlling an instruction cache including a least-recently-used bits array, a tag array, and a data array, includes looking up, in the least-recently-used bits array, least-recently-used bits for each of a plurality of cacheline sets in the instruction cache, determining a most-recently-used way in a designated cacheline set of the plurality of cacheline sets based on the least-recently-used bits for the designated cacheline, looking up, in the tag array, tags for one or more ways in the designated cacheline set, looking up, in the data array, data stored in the most-recently-used way in the designated cacheline set, and if there is a cache hit in the most-recently-used way, retrieving the data stored in the most-recently-used way from the data array.

摘要翻译： 在一个实施例中，一种用于控制包括最近最少使用的位阵列，标签阵列和数据阵列的指令高速缓存的方法包括在最近最少使用的位阵列中查找最近最少使用的位 对于指令高速缓存中的多个高速缓存行集合中的每一个，基于指定的高速缓存行的最近最少使用的比特来确定在多个高速缓存行集合的指定的高速缓存行集合中的最近使用的方式，查找 标签数组，在指定的高速缓存行集中的一种或多种方式的标签，在数据数组中查找，以指定的高速缓存行集合中最近使用的方式存储的数据，以及如果最多存在高速缓存命中 以最常用的方式，从数据数组中检索以最近使用的方式存储的数据。

公开(公告)号：US10241810B2

公开(公告)日：2019-03-26

申请号：US13475755

申请日：2012-05-18

申请人： Rupert Brauch ,  Madhu Swarna ,  Ross Segelken ,  David Dunn ,  Ben Hertzberg

发明人： Rupert Brauch ,  Madhu Swarna ,  Ross Segelken ,  David Dunn ,  Ben Hertzberg

IPC分类号： G06F9/30 ,  G06F9/455

摘要： A processing system comprising a microprocessor core and a translator. Within the microprocessor core is arranged a hardware decoder configured to selectively decode instructions for execution in the microprocessor core, and, a logic structure configured to track usage of the hardware decoder. The translator is operatively coupled to the logic structure and configured to selectively translate the instructions for execution in the microprocessor core, based on the usage of the hardware decoder as determined by the logic structure.