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公开(公告)号：US20200219655A1
公开(公告)日：2020-07-09
申请号：US16239500
申请日：2019-01-03
Inventor： Shao-Wei Peng , Hung-Ting Chou , Chien-Te Yu
Abstract: A capacitor array with staggered-layer structure includes a plurality of capacitor units. Each of the plurality of capacitor units comprises a plurality of odd layers formed with a first slot; a first via formed in the first slot; a plurality of first connecting portion configured to connect the first via and the plurality of odd layers; a plurality of even layers formed with a second slot; a second via formed in the second slot; a plurality of second connecting portion configured to connect the second via and the plurality of even layers; wherein one of the plurality of odd layers is adjacent to one of the plurality of even layers to form a staggered-layer structure.
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公开(公告)号：US10298182B1
公开(公告)日：2019-05-21
申请号：US15846719
申请日：2017-12-19
Inventor： Chia-Jen Liang , Yen-Cheng Kuan , Ching-Wen Chiang , Hung-Ting Chou
Abstract: A radio frequency amplifier comprises a transistor, a transformer and a variable capacitor. The transistor has an input terminal, an output terminal and a control terminal. The transformer has a first coil conductor and a second coil conductor. The first coil conductor magnetically couples to the second coil conductor. The second coil conductor connects to the control terminal. The first coil conductor connects to the input terminal. The variable capacitor connects in parallel with the second coil conductor. An integrated circuit using the radio frequency amplifier is also introduced.
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公开(公告)号：US10277170B1
公开(公告)日：2019-04-30
申请号：US15846671
申请日：2017-12-19
Inventor： Chia-Jen Liang , Yen-Cheng Kuan , Ching-Wen Chiang , Hung-Ting Chou
Abstract: A radio frequency amplifier comprises a transistor, a transformer and a variable capacitor. The transistor has an input terminal, an output terminal and a control terminal. The transformer has a first coil conductor and a second coil conductor. The first coil conductor magnetically couples to the second coil conductor. The second coil conductor connects to the control terminal. The first coil conductor connects to the input terminal. The variable capacitor connects in parallel with the second coil conductor. The radio frequency amplifier is configured to be an input or output stage of an integrated circuit. An integrated circuit using the radio frequency amplifier is also introduced.
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Patent Agency Ranking
公开(公告)号：US10097389B1
公开(公告)日：2018-10-09
申请号：US15830019
申请日：2017-12-04
Inventor： Hong-Yeh Chang , Xiang Lin , Chien-Te Yu , Hung-Ting Chou
Abstract: A reflective modulator comprises a coupler, two diodes and two DC block units. The coupler has an input end used to output an output signal, an output end used to output an output signal, a first load end connected to one of the diodes and a second load end connected to another one of the diodes. The DC block units connect between the diodes and the coupler for DC blocking. A message signal is selectively inputted to both of the two DC block units for operating the state of the two diodes. A BPSK modulator using the reflective modulator and a quadrature modulator using the BPSK modulator are also introduced.
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公开(公告)号：US10097284B1
公开(公告)日：2018-10-09
申请号：US15846792
申请日：2017-12-19
Inventor： Yen-Cheng Kuan , Hung-Ting Chou
Abstract: An I/Q imbalance calibration method includes sequentially inputting a first in-phase and quadrature signals calibration signal to a front-end circuit of the transmitter system to acquire and estimate a first and second calibration signal strengths sequentially, wherein a delta estimation is adopted; calculating an I/Q gain imbalance according to estimated first and second calibration signal strengths; sequentially inputting a second in-phase calibration signal and both of the second in-phase and quadrature calibration signal to the front-end circuit of the transmitter system to acquire and estimate a third and fourth calibration signal strengths sequentially, wherein an I/Q gain imbalance compensation is formed on the first in-phase and quadrature calibration signals to generate the second in-phase and quadrature calibration signals; and calculating an I/Q phase imbalance according to estimated third and fourth calibration signal strengths.
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公开(公告)号：US10476717B1
公开(公告)日：2019-11-12
申请号：US16234484
申请日：2018-12-27
Inventor： Tao Wang , Hung-Ting Chou , Chien-Te Yu , Ching-I Chien
Abstract: A vector modulator includes a quadrature component generator, configured to generate an input in-phase signal and an input quadrature signal according to an input radio frequency (RF) signal; a switching circuit, receiving a plurality of bits, comprising a plurality of switches controlled by the plurality of bits, configured to generate an output in-phase signal and an output quadrature signal according to the plurality of bits, where the output in-phase signal and the output quadrature signal are related to input in-phase signal and the input quadrature signal; and a combining module, configured to generate an output RF signal according to the output in-phase signal and the output quadrature signal.
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公开(公告)号：US10284289B1
公开(公告)日：2019-05-07
申请号：US15847967
申请日：2017-12-20
Inventor： Hong-Yeh Chang , Xiang Lin , Chien-Te Yu , Hung-Ting Chou
IPC: H04B10/07 , H04B10/071 , H04B10/516 , H04L27/20
Abstract: A reflective modulator which comprises a coupler, two diodes and two DC block units. The coupler has an input end used to output an output signal, an output end used to output an output signal, a first load end connected to one of the diodes and a second load end connected to another one of the diodes. The DC block units connect between the diodes and the coupler for DC blocking. A message signal is selectively inputted to both of the two DC block units for operating the state of the two diodes. The two diodes turn on when the message signal is large enough. The two diodes turn off when the message signal is not large enough. The two diodes are implemented by PIN diodes. A BPSK modulator using the reflective modulator and a quadrature modulator using the BPSK modulator is also introduced.
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公开(公告)号：US10069577B1
公开(公告)日：2018-09-04
申请号：US15848002
申请日：2017-12-20
Inventor： Yen-Cheng Kuan , Hung-Ting Chou
Abstract: An I/Q imbalance calibration method includes sequentially inputting a first in-phase and quadrature signals calibration signal to a front-end circuit of the transmitter system to acquire and estimate a first and second calibration signal strengths sequentially, wherein a delta estimation is adopted; calculating an I/Q gain imbalance according to estimated first and second calibration signal strengths; sequentially inputting a second in-phase calibration signal and both of the second in-phase and quadrature calibration signal to the front-end circuit of the transmitter system to acquire and estimate a third and fourth calibration signal strengths sequentially, wherein an I/Q gain imbalance compensation is formed on the first in-phase and quadrature calibration signals to generate the second in-phase and quadrature calibration signals; and calculating an I/Q phase imbalance according to estimated third and fourth calibration signal strengths.
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