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公开(公告)号：US08692575B2
公开(公告)日：2014-04-08
申请号：US13271179
申请日：2011-10-11
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： G06F7/388
摘要： A family of self-timed, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level. The elements pass information by means of state tokens, rather than voltages. Each cell is self-timed, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, the edges receiving state tokens from neighboring logic elements and transferring output state tokens to neighboring logic elements, and circuitry configured to perform, when the circuitry inputs contain valid tokens and the circuitry outputs are empty, a logic operation utilizing received tokens as inputs, thereby producing an output token reflecting the result of the logic operation.
摘要翻译： 与其最近邻居交互的自定时，电荷节省异步逻辑元件的系列允许在位级异步的电路的设计和实现。 元素通过状态令牌而不是电压传递信息。 每个单元都是自定时的，因此不需要硬件非本地连接。 异步逻辑元件包括用于与至少一个相邻单元进行异步通信的边缘集合，边缘从相邻逻辑元件接收状态令牌并将输出状态令牌传送到相邻逻辑元件，以及电路，其被配置为当电路输入包含有效 令牌和电路输出为空，逻辑操作利用接收的令牌作为输入，从而产生反映逻辑运算结果的输出令牌。
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公开(公告)号：US08035414B2
公开(公告)日：2011-10-11
申请号：US12422979
申请日：2009-04-13
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： G06F7/388
摘要： A family of reconfigurable, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements pass information by means of charge packets (tokens), rather than voltages. Each cell is self-timed, and cells that are configured as interconnect perform at propagation delay speeds, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, each edge having an input for receiving tokens from neighboring cells and an output for transferring an output charge packet to at least one neighboring cell, and circuitry configured to perform a logic operation utilizing received charge packets as inputs and to produce an output charge packet reflecting the result of the logic operation.
摘要翻译： 与其最近邻居交互的可重配置，电荷节省的异步逻辑元件系列允许设计和实现在位级别而不是功能块级异步的电路。 这些元件通过电荷分组（令牌）传递信息，而不是电压。 每个单元都是自定时的，配置为互连的单元以传播延迟速度执行，因此不需要硬件非本地连接。 异步逻辑元件包括用于与至少一个相邻小区异步通信的一组边缘，每个边缘具有用于从相邻小区接收令牌的输入和用于将输出电荷分组传送到至少一个相邻小区的输出，以及被配置为 利用接收的充电分组作为输入进行逻辑运算，并产生反映逻辑运算结果的输出电荷分组。
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公开(公告)号：US20100102848A1
公开(公告)日：2010-04-29
申请号：US12422979
申请日：2009-04-13
IPC分类号： H03K19/173
CPC分类号： G06F7/388
摘要： A family of reconfigurable, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements pass information by means of charge packets (tokens), rather than voltages. Each cell is self-timed, and cells that are configured as interconnect perform at propagation delay speeds, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, each edge having an input for receiving tokens from neighboring cells and an output for transferring an output charge packet to at least one neighboring cell, and circuitry configured to perform a logic operation utilizing received charge packets as inputs and to produce an output charge packet reflecting the result of the logic operation.
摘要翻译： 与其最近邻居交互的可重配置，电荷节省的异步逻辑元件系列允许设计和实现在位级别而不是功能块级异步的电路。 这些元件通过电荷分组（令牌）传递信息，而不是电压。 每个单元都是自定时的，配置为互连的单元以传播延迟速度执行，因此不需要硬件非本地连接。 异步逻辑元件包括用于与至少一个相邻小区异步通信的一组边缘，每个边缘具有用于从相邻小区接收令牌的输入和用于将输出电荷分组传送到至少一个相邻小区的输出，以及被配置为 利用接收的充电分组作为输入进行逻辑运算，并产生反映逻辑运算结果的输出电荷分组。
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公开(公告)号：US20120025868A1
公开(公告)日：2012-02-02
申请号：US13271179
申请日：2011-10-11
IPC分类号： H03K19/173
CPC分类号： G06F7/388
摘要： A family of self-timed, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level. The elements pass information by means of state tokens, rather than voltages. Each cell is self-timed, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, the edges receiving state tokens from neighboring logic elements and transferring output state tokens to neighboring logic elements, and circuitry configured to perform, when the circuitry inputs contain valid tokens and the circuitry outputs are empty, a logic operation utilizing received tokens as inputs, thereby producing an output token reflecting the result of the logic operation.
摘要翻译： 与其最近邻居交互的自定时，电荷节省异步逻辑元件的系列允许在位级异步的电路的设计和实现。 元素通过状态令牌而不是电压传递信息。 每个单元都是自定时的，因此不需要硬件非本地连接。 异步逻辑元件包括用于与至少一个相邻单元进行异步通信的边缘集合，边缘从相邻逻辑元件接收状态令牌并将输出状态令牌传送到相邻逻辑元件，以及电路，其被配置为当电路输入包含有效 令牌和电路输出为空，逻辑操作利用接收的令牌作为输入，从而产生反映逻辑运算结果的输出令牌。
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公开(公告)号：US08013629B2
公开(公告)日：2011-09-06
申请号：US12561262
申请日：2009-09-16
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/173 , G06F7/388 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17748
摘要： A family of reconfigurable asynchronous logic elements that interact with their nearest neighbors permits reconfigurable implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements pass information by means of tokens. Each cell is self-timed, and cells that are configured as interconnect perform at propagation delay speeds, so no hardware non-local connections are needed. A reconfigurable asynchronous logic element comprises a set of edges for communication with at least one neighboring cell, each edge having an input for receiving tokens from neighboring cells and an output for transferring tokens to at least one neighboring cell, circuitry configured to perform a logic operation utilizing received tokens as inputs and to produce an output token reflecting the result of the logic operation, and circuitry. A reconfigurable lattice of asynchronous logic automata comprises a plurality of reconfigurable logic automata that compute by locally passing state tokens and are reconfigured by the directed shifting of programming instructions through neighboring logic elements.
摘要翻译： 与其最近邻居交互的一系列可重新配置的异步逻辑元件允许在位级而不是功能块级的异步电路的可重构实现。 这些元素通过令牌传递信息。 每个单元都是自定时的，配置为互连的单元以传播延迟速度执行，因此不需要硬件非本地连接。 可重新配置的异步逻辑元件包括用于与至少一个相邻小区进行通信的边缘集合，每个边缘具有用于从相邻小区接收令牌的输入和用于将令牌传送到至少一个相邻小区的输出，被配置为执行逻辑运算 利用接收到的令牌作为输入并产生反映逻辑运算结果的输出令牌和电路。 异步逻辑自动机的可重新格式包括多个可重新配置的逻辑自动机，其通过本地传递状态令牌来计算，并且通过相邻逻辑元件的编程指令的定向移位来重新配置。
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公开(公告)号：US20100185837A1
公开(公告)日：2010-07-22
申请号：US12561262
申请日：2009-09-16
IPC分类号： G06F9/305 , H03K19/173
CPC分类号： H03K19/173 , G06F7/388 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17748
摘要： A family of reconfigurable asynchronous logic elements that interact with their nearest neighbors permits reconfigurable implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements pass information by means of tokens. Each cell is self-timed, and cells that are configured as interconnect perform at propagation delay speeds, so no hardware non-local connections are needed. A reconfigurable asynchronous logic element comprises a set of edges for communication with at least one neighboring cell, each edge having an input for receiving tokens from neighboring cells and an output for transferring tokens to at least one neighboring cell, circuitry configured to perform a logic operation utilizing received tokens as inputs and to produce an output token reflecting the result of the logic operation, and circuitry. A reconfigurable lattice of asynchronous logic automata comprises a plurality of reconfigurable logic automata that compute by locally passing state tokens and are reconfigured by the directed shifting of programming instructions through neighboring logic elements.
摘要翻译： 与其最近邻居交互的一系列可重新配置的异步逻辑元件允许在位级而不是功能块级的异步电路的可重构实现。 这些元素通过令牌传递信息。 每个单元都是自定时的，配置为互连的单元以传播延迟速度执行，因此不需要硬件非本地连接。 可重新配置的异步逻辑元件包括用于与至少一个相邻小区通信的一组边缘，每个边缘具有用于从相邻小区接收令牌的输入和用于向至少一个相邻小区传送令牌的输出，被配置为执行逻辑运算的电路 利用接收到的令牌作为输入并产生反映逻辑运算结果的输出令牌和电路。 异步逻辑自动机的可重新格式包括多个可重新配置的逻辑自动机，其通过本地传递状态令牌来计算，并且通过相邻逻辑元件的编程指令的定向移位来重新配置。
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公开(公告)号：US20120062277A1
公开(公告)日：2012-03-15
申请号：US13226484
申请日：2011-09-06
IPC分类号： H03K19/173
CPC分类号： H03K19/173 , G06F7/388 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17748
摘要： A family of reconfigurable asynchronous logic elements that interact with their nearest neighbors permits reconfigurable implementation of circuits that are asynchronous at the bit level. A reconfigurable asynchronous logic cell comprises a set of one-bit buffers for communication with at least one neighboring cell, each buffer capable of having several states and configured for receiving input state tokens from neighboring cells and for transferring output state tokens to neighboring cells, and a one-bit processor configured to perform a logic operation utilizing received tokens as inputs and to produce an output token reflecting the result of the logic operation, wherein the logic operation and the functional configuration of the buffers are reconfigurably programmable. A reconfigurable logic circuit comprises a plurality of reconfigurable logic cells that compute by locally passing state tokens and are reconfigured by the directed shifting of programming instructions through neighboring logic cells.
摘要翻译： 与其最近的邻居交互的可重新配置的异步逻辑元件系列允许在位级异步的电路的可重构实现。 可重新配置的异步逻辑单元包括一组用于与至少一个相邻单元进行通信的缓冲器，每个缓冲器能够具有多个状态并被配置用于从相邻小区接收输入状态令牌并将输出状态令牌传送到相邻小区，以及 配置为执行利用接收的令牌作为输入的逻辑操作并产生反映逻辑操作的结果的输出令牌的一位处理器，其中缓冲器的逻辑操作和功能配置可重新配置地可编程。 可重配置逻辑电路包括多个可重构逻辑单元，其通过本地通过状态令牌来计算，并且通过相邻逻辑单元的编程指令的定向移位来重新配置。
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公开(公告)号：US08766665B2
公开(公告)日：2014-07-01
申请号：US13226484
申请日：2011-09-06
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/173 , G06F7/388 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17748
摘要： A family of reconfigurable asynchronous logic elements that interact with their nearest neighbors permits reconfigurable implementation of circuits that are asynchronous at the bit level. A reconfigurable asynchronous logic cell comprises a set of one-bit buffers for communication with at least one neighboring cell, each buffer capable of having several states and configured for receiving input state tokens from neighboring cells and for transferring output state tokens to neighboring cells, and a one-bit processor configured to perform a logic operation utilizing received tokens as inputs and to produce an output token reflecting the result of the logic operation, wherein the logic operation and the functional configuration of the buffers are reconfigurably programmable. A reconfigurable logic circuit comprises a plurality of reconfigurable logic cells that compute by locally passing state tokens and are reconfigured by the directed shifting of programming instructions through neighboring logic cells.
摘要翻译： 与其最近的邻居交互的可重新配置的异步逻辑元件系列允许在位级异步的电路的可重构实现。 可重新配置的异步逻辑单元包括一组用于与至少一个相邻单元进行通信的缓冲器，每个缓冲器能够具有多个状态并被配置用于从相邻小区接收输入状态令牌并将输出状态令牌传送到相邻小区，以及 配置为执行利用接收的令牌作为输入的逻辑操作并产生反映逻辑操作的结果的输出令牌的一位处理器，其中缓冲器的逻辑操作和功能配置可重新配置地可编程。 可重配置逻辑电路包括多个可重构逻辑单元，其通过本地通过状态令牌来计算，并且通过相邻逻辑单元的编程指令的定向移位来重新配置。
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