-
公开(公告)号：US08035414B2
公开(公告)日：2011-10-11
申请号：US12422979
申请日：2009-04-13
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： G06F7/388
摘要： A family of reconfigurable, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements pass information by means of charge packets (tokens), rather than voltages. Each cell is self-timed, and cells that are configured as interconnect perform at propagation delay speeds, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, each edge having an input for receiving tokens from neighboring cells and an output for transferring an output charge packet to at least one neighboring cell, and circuitry configured to perform a logic operation utilizing received charge packets as inputs and to produce an output charge packet reflecting the result of the logic operation.
摘要翻译： 与其最近邻居交互的可重配置，电荷节省的异步逻辑元件系列允许设计和实现在位级别而不是功能块级异步的电路。 这些元件通过电荷分组（令牌）传递信息，而不是电压。 每个单元都是自定时的，配置为互连的单元以传播延迟速度执行，因此不需要硬件非本地连接。 异步逻辑元件包括用于与至少一个相邻小区异步通信的一组边缘，每个边缘具有用于从相邻小区接收令牌的输入和用于将输出电荷分组传送到至少一个相邻小区的输出，以及被配置为 利用接收的充电分组作为输入进行逻辑运算，并产生反映逻辑运算结果的输出电荷分组。
-
公开(公告)号：US20100102848A1
公开(公告)日：2010-04-29
申请号：US12422979
申请日：2009-04-13
IPC分类号： H03K19/173
CPC分类号： G06F7/388
摘要： A family of reconfigurable, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements pass information by means of charge packets (tokens), rather than voltages. Each cell is self-timed, and cells that are configured as interconnect perform at propagation delay speeds, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, each edge having an input for receiving tokens from neighboring cells and an output for transferring an output charge packet to at least one neighboring cell, and circuitry configured to perform a logic operation utilizing received charge packets as inputs and to produce an output charge packet reflecting the result of the logic operation.
摘要翻译： 与其最近邻居交互的可重配置，电荷节省的异步逻辑元件系列允许设计和实现在位级别而不是功能块级异步的电路。 这些元件通过电荷分组（令牌）传递信息，而不是电压。 每个单元都是自定时的，配置为互连的单元以传播延迟速度执行，因此不需要硬件非本地连接。 异步逻辑元件包括用于与至少一个相邻小区异步通信的一组边缘，每个边缘具有用于从相邻小区接收令牌的输入和用于将输出电荷分组传送到至少一个相邻小区的输出，以及被配置为 利用接收的充电分组作为输入进行逻辑运算，并产生反映逻辑运算结果的输出电荷分组。
-
公开(公告)号：US08692575B2
公开(公告)日：2014-04-08
申请号：US13271179
申请日：2011-10-11
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： G06F7/388
摘要： A family of self-timed, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level. The elements pass information by means of state tokens, rather than voltages. Each cell is self-timed, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, the edges receiving state tokens from neighboring logic elements and transferring output state tokens to neighboring logic elements, and circuitry configured to perform, when the circuitry inputs contain valid tokens and the circuitry outputs are empty, a logic operation utilizing received tokens as inputs, thereby producing an output token reflecting the result of the logic operation.
摘要翻译： 与其最近邻居交互的自定时，电荷节省异步逻辑元件的系列允许在位级异步的电路的设计和实现。 元素通过状态令牌而不是电压传递信息。 每个单元都是自定时的，因此不需要硬件非本地连接。 异步逻辑元件包括用于与至少一个相邻单元进行异步通信的边缘集合，边缘从相邻逻辑元件接收状态令牌并将输出状态令牌传送到相邻逻辑元件，以及电路，其被配置为当电路输入包含有效 令牌和电路输出为空，逻辑操作利用接收的令牌作为输入，从而产生反映逻辑运算结果的输出令牌。
-
公开(公告)号：US20120025868A1
公开(公告)日：2012-02-02
申请号：US13271179
申请日：2011-10-11
IPC分类号： H03K19/173
CPC分类号： G06F7/388
摘要： A family of self-timed, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level. The elements pass information by means of state tokens, rather than voltages. Each cell is self-timed, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, the edges receiving state tokens from neighboring logic elements and transferring output state tokens to neighboring logic elements, and circuitry configured to perform, when the circuitry inputs contain valid tokens and the circuitry outputs are empty, a logic operation utilizing received tokens as inputs, thereby producing an output token reflecting the result of the logic operation.
摘要翻译： 与其最近邻居交互的自定时，电荷节省异步逻辑元件的系列允许在位级异步的电路的设计和实现。 元素通过状态令牌而不是电压传递信息。 每个单元都是自定时的，因此不需要硬件非本地连接。 异步逻辑元件包括用于与至少一个相邻单元进行异步通信的边缘集合，边缘从相邻逻辑元件接收状态令牌并将输出状态令牌传送到相邻逻辑元件，以及电路，其被配置为当电路输入包含有效 令牌和电路输出为空，逻辑操作利用接收的令牌作为输入，从而产生反映逻辑运算结果的输出令牌。
-
公开(公告)号：US08742794B2
公开(公告)日：2014-06-03
申请号：US12422491
申请日：2009-04-13
申请人： Neil Gershenfeld , Kailiang Chen , Jonathan Leu
发明人： Neil Gershenfeld , Kailiang Chen , Jonathan Leu
IPC分类号： H03K19/173 , G06G7/28
CPC分类号： G06F7/388
摘要： A distributed, reconfigurable statistical signal processing apparatus comprises an array of discrete-time analog signal processing circuitry for statistical signal processing based on a local message-passing algorithm and digital configuration circuitry for controlling the functional behavior of the array of analog circuitry. The input signal to the apparatus may be expressed as a probabilistic representation. The analog circuitry may comprise computational elements arranged in a network, with a receiving module that assigns probability values when an input signal arrives and communicates the probability values to one of the computational elements, the computational elements producing outputs based on the assigned probability values. The signal processing apparatus may be an analog logic automata cell or an array of cells, wherein each cell is able to communicate with all neighboring cells.
摘要翻译： 分布式可重新配置的统计信号处理装置包括用于基于本地消息传递算法的统计信号处理的离散时间模拟信号处理电路阵列和用于控制模拟电路阵列的功能行为的数字配置电路。 到装置的输入信号可以表示为概率表示。 模拟电路可以包括布置在网络中的计算元件，其中接收模块在输入信号到达时分配概率值，并将概率值传送到计算元件之一，计算元件基于分配的概率值产生输出。 信号处理装置可以是模拟逻辑自动机单元或单元阵列，其中每个单元能够与所有相邻单元进行通信。
-
公开(公告)号：US20100033228A1
公开(公告)日：2010-02-11
申请号：US12422491
申请日：2009-04-13
申请人： Neil Gershenfeld , Kailiang Chen , Jonathan Leu
发明人： Neil Gershenfeld , Kailiang Chen , Jonathan Leu
IPC分类号： G06G7/28
CPC分类号： G06F7/388
摘要： A distributed, reconfigurable statistical signal processing apparatus comprises an array of discrete-time analog signal processing circuitry for statistical signal processing based on a local message-passing algorithm and digital configuration circuitry for controlling the functional behavior of the array of analog circuitry. The input signal to the apparatus may be expressed as a probabilistic representation. The analog circuitry may comprise computational elements arranged in a network, with a receiving module that assigns probability values when an input signal arrives and communicates the probability values to one of the computational elements, the computational elements producing outputs based on the assigned probability values. The signal processing apparatus may be an analog logic automata cell or an array of cells, wherein each cell is able to communicate with all neighboring cells.
摘要翻译： 分布式可重新配置的统计信号处理装置包括用于基于本地消息传递算法的统计信号处理的离散时间模拟信号处理电路阵列和用于控制模拟电路阵列的功能行为的数字配置电路。 到装置的输入信号可以表示为概率表示。 模拟电路可以包括布置在网络中的计算元件，其中接收模块在输入信号到达时分配概率值，并将概率值传送到计算元件之一，计算元件基于分配的概率值产生输出。 信号处理装置可以是模拟逻辑自动机单元或单元阵列，其中每个单元能够与所有相邻单元进行通信。
-
公开(公告)号：US08350614B2
公开(公告)日：2013-01-08
申请号：US12422491
申请日：2009-04-13
申请人： Neil Gershenfeld , Kailiang Chen , Jonathan Leu
发明人： Neil Gershenfeld , Kailiang Chen , Jonathan Leu
IPC分类号： H03K19/173 , G06G7/28
摘要： A distributed, reconfigurable statistical signal processing apparatus comprises an array of discrete-time analog signal processing circuitry for statistical signal processing based on a local message-passing algorithm and digital configuration circuitry for controlling the functional behavior of the array of analog circuitry. The input signal to the apparatus may be expressed as a probabilistic representation. The analog circuitry may comprise computational elements arranged in a network, with a receiving module that assigns probability values when an input signal arrives and communicates the probability values to one of the computational elements, the computational elements producing outputs based on the assigned probability values. The signal processing apparatus may be an analog logic automata cell or an array of cells, wherein each cell is able to communicate with all neighboring cells.
-
公开(公告)号：US20190149109A1
公开(公告)日：2019-05-16
申请号：US16244934
申请日：2019-01-10
申请人： Amandeep Singh , Kailiang Chen , Tyler S. Ralston
发明人： Amandeep Singh , Kailiang Chen , Tyler S. Ralston
CPC分类号： H03F3/45179 , G01N29/2406 , G01N29/44 , G01N29/4463 , G01N29/449 , H03F3/345 , H03F2200/129 , H03F2203/45116 , H03F2203/45524 , H03M1/124 , H03M1/38
摘要： An ultrasound circuit comprising a single-ended trans-impedance amplifier (TIA) is described, The TIA is coupled to an ultrasonic transducer to amplify an electrical signal generated by the ultrasonic transducer in response to receiving an ultrasound signal. The TEA is followed by further processing circuitry configured to filter, amplify, and digitize the signal produced by the TIA.
-
9.发明申请公开(公告)号：US20190299251A1
公开(公告)日：2019-10-03
申请号：US16443931
申请日：2019-06-18
申请人： Chao Chen , Kailiang Chen , Leung Kin Chiu , Youn-Jae Kook , Keith G. Fife
发明人： Chao Chen , Kailiang Chen , Leung Kin Chiu , Youn-Jae Kook , Keith G. Fife
摘要： Aspects of technology described herein relate to ultrasound apparatuses including capacitive micromachines ultrasonic transducers (CMUTs) that are directly electrically coupled to delta-sigma analog-to-digital converters (ADCs). The apparatus may lack an amplifier or multiplexer between each CMUT and delta-sigma ADC. The apparatus may include between 100 and 20,000 CMUTs and between 100 and 20,000 delta-sigma ADCs, each of the CMUTs directly electrically coupled to one of the delta-sigma ADCs. The CMUTs and the delta-sigma ADCs may be monolithically integrated on a single substrate. The delta-sigma ADCs may lack an integrator distinct from the CMUT. An internal capacitance of the CMUT may serve as an integrator for the delta-sigma ADC.
-
公开(公告)号：US20180367110A1
公开(公告)日：2018-12-20
申请号：US16011742
申请日：2018-06-19
申请人： Amandeep Singh , Kailiang Chen , Tyler S. Ralston
发明人： Amandeep Singh , Kailiang Chen , Tyler S. Ralston
摘要： An ultrasound circuit comprising a single-ended trans-impedance amplifier (TIA) is described. The TIA is coupled to an ultrasonic transducer to amplify an electrical signal generated by the ultrasonic transducer in response to receiving an ultrasound signal. The TIA is followed by further processing circuitry configured to filter, amplify, and digitize the signal produced by the TIA.
-
-
-
-
-
-
-
-
-
搜索结果
21 条记录 (耗时 0.022 秒)
