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公开(公告)号：US09413407B2
公开(公告)日：2016-08-09
申请号：US13178559
申请日：2011-07-08
申请人： Jan van Sinderen , Johannes Hubertus Antonius Brekelmans , Frank Harald Erich Ho Chung Leong , Nenad Pavlovic
发明人： Jan van Sinderen , Johannes Hubertus Antonius Brekelmans , Frank Harald Erich Ho Chung Leong , Nenad Pavlovic
摘要： The invention relates to frequency conversion systems, in particular for use as up-converters or down-converters in radiofrequency (RF) receivers or transmitters, exemplary embodiments including a radiofrequency receiver including an RF signal input; a mixing module including a first plurality of IF amplifiers each connected to the RF signal input via a switch; a multi-phase local oscillator signal generator configured to provide a switching signal to each switch; and a summing module configured to receive output signals from each of the IF amplifiers and to provide a second plurality of output IF signals from a weighted sum of the IF amplifier output signals, wherein the second plurality is different to the first plurality.
摘要翻译： 本发明涉及频率转换系统，特别是用作射频（RF）接收机或发射机中的上转换器或下变频器，包括射频信号输入的射频接收机的示例性实施例; 混合模块，其包括经由开关连接到RF信号输入的第一多个IF放大器; 配置为向每个开关提供切换信号的多相本地振荡器信号发生器; 以及求和模块，被配置为从每个IF放大器接收输出信号，并且从IF放大器输出信号的加权和提供第二多个输出IF信号，其中第二多个不同于第一多个。
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公开(公告)号：US20120008717A1
公开(公告)日：2012-01-12
申请号：US13178559
申请日：2011-07-08
申请人： Jan van Sinderen , Johannes Hubertus Antonius Brekelmans , Frank Harald Erich Ho Chung Leong , Nenad Pavlovic
发明人： Jan van Sinderen , Johannes Hubertus Antonius Brekelmans , Frank Harald Erich Ho Chung Leong , Nenad Pavlovic
摘要： The invention relates to frequency conversion systems, in particular for use as up-converters or down-converters in radiofrequency (RF) receivers or transmitters, exemplary embodiments including a radiofrequency receiver (1000) comprising: an RF signal input (1001); a mixing module (1002) comprising a first plurality of IF amplifiers (10041-3) each connected to the RF signal input (1001) via a switch (10031-3); a multi-phase local oscillator signal generator (1300) configured to provide a switching signal to each switch (10031-3); and a summing module (1005) configured to receive output signals from each of the IF amplifiers (10041-3) and to provide a second plurality of output IF signals from a weighted sum of the IF amplifier output signals, wherein the second plurality is different to the first plurality.
摘要翻译： 本发明涉及频率转换系统，特别是用作射频（RF）接收机或发射机中的上转换器或下变频器，包括射频接收机（1000）的示例性实施例包括：RF信号输入（1001）; 混合模块（1002），包括经由开关（10031-3）连接到RF信号输入（1001）的第一多个IF放大器（10041-3）; 配置为向每个开关（10031-3）提供切换信号的多相本地振荡器信号发生器（1300）; 以及被配置为从每个IF放大器（10041-3）接收输出信号并从IF放大器输出信号的加权和提供第二多个输出IF信号的求和模块（1005），其中第二多个不同 到第一个多个。
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公开(公告)号：US20110291732A1
公开(公告)日：2011-12-01
申请号：US13116967
申请日：2011-05-26
IPC分类号： G06F1/04
CPC分类号： G06F1/025
摘要： The invention relates to a digital signal generator for providing one or more phases of a local oscillator signal for use in digital to analogue converters and harmonic rejection mixers. Embodiments disclosed include a local oscillator signal generator (200) for a mixer of a radiofrequency receiver, the signal generator (200) comprising a bit sequence generator (201) having a plurality of parallel output lines (203), a digital signal generator (202) having a serial output line (204) and a plurality of input lines connected to respective output lines (203) of the bit sequence generator (201) and a clock signal input line (205), wherein the digital signal generator (202) is configured to provide an output bit sequence on the serial output line (204) at a rate given by a clock signal provided on the clock signal input line (205) and a sequence given by a sequence of bits from the bit sequence generator (201) on the plurality of input lines (203).
摘要翻译： 本发明涉及用于提供用于数模转换器和谐波抑制混频器的本地振荡器信号的一个或多个相位的数字信号发生器。 所公开的实施例包括用于射频接收机的混频器的本地振荡器信号发生器（200），所述信号发生器（200）包括具有多个并行输出线（203）的位序发生器（201），数字信号发生器 ）和连接到位序发生器（201）的相应输出线（203）的多条输入线和时钟信号输入线（205），其中数字信号发生器（202）是 被配置为以由在时钟信号输入线（205）上提供的时钟信号给出的速率和由位序列发生器（201）的位序列给出的序列在串行输出线（204）上提供输出比特序列， 在多个输入线（203）上。
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公开(公告)号：US08638174B2
公开(公告)日：2014-01-28
申请号：US13116967
申请日：2011-05-26
CPC分类号： G06F1/025
摘要： The invention relates to a digital signal generator for providing one or more phases of a local oscillator signal for use in digital to analogue converters and harmonic rejection mixers. Embodiments disclosed include a local oscillator signal generator (200) for a mixer of a radiofrequency receiver, the signal generator (200) comprising a bit sequence generator (201) having a plurality of parallel output lines (203), a digital signal generator (202) having a serial output line (204) and a plurality of input lines connected to respective output lines (203) of the bit sequence generator (201) and a clock signal input line (205), wherein the digital signal generator (202) is configured to provide an output bit sequence on the serial output line (204) at a rate given by a clock signal provided on the clock signal input line (205) and a sequence given by a sequence of bits from the bit sequence generator (201) on the plurality of input lines (203).
摘要翻译： 本发明涉及用于提供用于数模转换器和谐波抑制混频器的本地振荡器信号的一个或多个相位的数字信号发生器。 所公开的实施例包括用于射频接收机的混频器的本地振荡器信号发生器（200），所述信号发生器（200）包括具有多个并行输出线（203）的位序发生器（201），数字信号发生器 ）和连接到位序发生器（201）的相应输出线（203）的多条输入线和时钟信号输入线（205），其中数字信号发生器（202）是 被配置为以由在时钟信号输入线（205）上提供的时钟信号给出的速率和由位序列发生器（201）的位序列给出的序列在串行输出线（204）上提供输出比特序列， 在多个输入线（203）上。
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公开(公告)号：US20120105128A1
公开(公告)日：2012-05-03
申请号：US13266744
申请日：2010-04-23
申请人： Dennis Jeurissen , Gerben Willem de Jong , Jan van Sinderen , Johannes Hubertus Antonius Brekelmans
发明人： Dennis Jeurissen , Gerben Willem de Jong , Jan van Sinderen , Johannes Hubertus Antonius Brekelmans
IPC分类号： G06G7/12
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/1483 , H03D7/1491 , H03D2200/0086
摘要： An electronic device comprising a passive harmonic-rejection mixer (400) and a calibration circuitry (425). The passive harmonic rejection mixer has an input (102) connected to several sub-mixer stages (402), and the sub-mixer stages are connected to a summing module (406, 408) for generating the output (104). Each sub-mixing stage comprises a gating module (414), an amplifier (416), and a weighting module (418), the gating module selectively passing the input signal or the input signal with inverted polarity under the control of control signals. The calibration circuitry (425) is adapted to input a reference signal (430) to the input of the mixer, receive an output signal (104) from the output of the mixer, and set the weights (K1, K2, K3, K4) of the weighting modules to make the output signal match an expected output signal.
摘要翻译： 一种包括无源谐波抑制混频器（400）和校准电路（425）的电子设备。 无源谐波抑制混频器具有连接到多个子混频器级（402）的输入（102），并且子混频器级连接到用于产生输出（104）的求和模块（406,408）。 每个子混合级包括门控模块（414），放大器（416）和加权模块（418），门控模块在控制信号的控制下选择性地使输入信号或具有反相极性的输入信号。 校准电路（425）适于将参考信号（430）输入到混频器的输入端，从混频器的输出接收输出信号（104），并设定权重（K1，K2，K3，K4） 的加权模块以使输出信号匹配期望的输出信号。
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公开(公告)号：US08660508B2
公开(公告)日：2014-02-25
申请号：US13266744
申请日：2010-04-23
申请人： Dennis Jeurissen , Gerben Willem de Jong , Jan van Sinderen , Johannes Hubertus Antonius Brekelmans
发明人： Dennis Jeurissen , Gerben Willem de Jong , Jan van Sinderen , Johannes Hubertus Antonius Brekelmans
IPC分类号： H04B17/00
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/1483 , H03D7/1491 , H03D2200/0086
摘要： An electronic device comprising a passive harmonic-rejection mixer (400) and a calibration circuitry (425). The passive harmonic rejection mixer has an input (102) connected to several sub-mixer stages (402), and the sub-mixer stages are connected to a summing module (406, 408) for generating the output (104). Each sub-mixing stage comprises a gating module (414), an amplifier (416), and a weighting module (418), the gating module selectively passing the input signal or the input signal with inverted polarity under the control of control signals. The calibration circuitry (425) is adapted to input a reference signal (430) to the input of the mixer, receive an output signal (104) from the output of the mixer, and set the weights (K1, K2, K3, K4) of the weighting modules to make the output signal match an expected output signal.
摘要翻译： 一种包括无源谐波抑制混频器（400）和校准电路（425）的电子设备。 无源谐波抑制混频器具有连接到多个子混频器级（402）的输入（102），并且子混频器级连接到用于产生输出（104）的求和模块（406,408）。 每个子混合级包括门控模块（414），放大器（416）和加权模块（418），门控模块在控制信号的控制下选择性地使输入信号或具有反相极性的输入信号。 校准电路（425）适于将参考信号（430）输入到混频器的输入端，从混频器的输出接收输出信号（104），并设定权重（K1，K2，K3，K4） 的加权模块以使输出信号匹配期望的输出信号。
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公开(公告)号：US08138817B2
公开(公告)日：2012-03-20
申请号：US12738297
申请日：2008-10-29
申请人： Johannes Hubertus Antonius Brekelmans , Gerben Willem De Jong , Rachid El Waffaoui , Dennis Jeurissen , Jan Van Sinderen , Simon W K Lee
发明人： Johannes Hubertus Antonius Brekelmans , Gerben Willem De Jong , Rachid El Waffaoui , Dennis Jeurissen , Jan Van Sinderen , Simon W K Lee
IPC分类号： G06G7/12
CPC分类号： H03D7/165 , H03D7/18 , H03D2200/0082 , H03D2200/0086
摘要： An electronic device comprising a passive harmonic-rejection mixer. The passive harmonic rejection mixer has an input connected to several sub-mixer stages, and the sub-mixer stages are connected to a summing module for generating the output. Each sub-mixing stage comprises a gating module and a respective amplifier, the gating module adapted to selectively pass the input signal or the input signal with inverted polarity under the control of control signals.
摘要翻译： 一种包括无源谐波抑制混频器的电子设备。 无源谐波抑制混频器具有连接到多个子混频器级的输入，并且子混频器级连接到用于产生输出的求和模块。 每个子混合级包括门控模块和相应的放大器，门控模块适于在控制信号的控制下选择性地传递具有反相极性的输入信号或输入信号。
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公开(公告)号：US20090021332A1
公开(公告)日：2009-01-22
申请号：US11576808
申请日：2005-10-05
申请人： Johannes Hubertus Antonius Brekelmans , Vincent Rambeau , Jan Van Sinderen , Marc Godfriedus Marie Notten
发明人： Johannes Hubertus Antonius Brekelmans , Vincent Rambeau , Jan Van Sinderen , Marc Godfriedus Marie Notten
IPC分类号： H03J5/24
CPC分类号： H01L27/0805 , H01L27/0629 , H03H7/25 , H03J2200/10
摘要： An integrated variable capacitance with low losses comprises an array (1) of switched capacitors (2-8). When using an array (1) of switched capacitors (2-8) to form a quasi continuously variable capacitor, a continuity of capacitance as function of the digital control signal to the array (1) leads to overall behavior of the series resistance of the array (1) as function of the capacitance that for some applications may be undesirable. Therefore a topology for a switched array (1) is proposed that allows to set series resistance relatively independent from capacitance. The array (1) may be fully or partially integrated in tunable LC filters, also in TV tuners.
摘要翻译： 具有低损耗的集成可变电容包括开关电容器（2-8）的阵列（1）。 当使用开关电容器（2〜8）的阵列（1〜8）形成准连续可变电容器时，作为阵列（1）的数字控制信号的功能的电容的连续性导致了串联电阻 作为对于一些应用的电容的函数的数组（1）可能是不期望的。 因此，提出了一种用于开关阵列（1）的拓扑，其允许相对独立于电容设置串联电阻。 阵列（1）可以完全或部分地集成在可调LC滤波器中，也可以在电视调谐器中。
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公开(公告)号：US08378720B2
公开(公告)日：2013-02-19
申请号：US13002818
申请日：2009-07-07
IPC分类号： H03B19/00
CPC分类号： H03K23/54
摘要： A signal processing arrangement comprises a series of latches (XDL, L1, L2) arranged as a clocked delay line (CDL) having a data input and a data output that are coupled to each other so as to form an inverting loop. An enable circuit (ACDL) allows or prevents a latch (L2) in the series of latches from changing state depending on whether, one clock cycle ago, the latch concerned received a given binary value or the inverse of that given binary 5 value, respectively, from the preceding latch (L1) in the series of latches. Such a circuit configuration allows a low-cost frequency division by an odd number with relatively small duty cycle errors.
摘要翻译： 信号处理装置包括被布置为具有数据输入的时钟延迟线（CDL）的一系列锁存器（XDL，L1，L2）和彼此耦合以形成反相环路的数据输出。 使能电路（ACDL）允许或防止一系列锁存器中的锁存器（L2）根据一个时钟周期之前的锁存器是否分别接收到给定的二进制值或者给定的二进制值5的反相来改变状态 ，从一系列闩锁中的先前锁存（L1）开始。 这种电路配置允许以相对小的占空比误差的低成本分频奇数。
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10.发明授权Device for receiving a RF signal with loop-through output and method for looping a RF input signal through a device for receiving RF signals 有权用于接收具有环通输出的RF信号的装置以及用于通过用于接收RF信号的装置对RF输入信号进行环路的方法公开(公告)号：US08207878B2
公开(公告)日：2012-06-26
申请号：US12744693
申请日：2008-11-24
IPC分类号： H03M1/10
摘要： A device for receiving a RF signal (1; 21) with loop-through output (16) is provided. The device comprises: an input (3) receiving a RF input signal (2); an analog-digital converter (8) converting the RF input signal (2) to a digital signal (9); a digital signal processing unit (10) digitally processing the digital signal (9); a digital-analog converter (14) converting the processed digital signal (13) to a loop-through RF signal (15) corresponding to the RF input signal (2); and a loop-through output (16) outputting the loop-through RF signal (15).
摘要翻译： 提供了一种用于接收具有环通输出（16）的RF信号（1; 21）的装置。 该装置包括：接收RF输入信号的输入端（3）; 将所述RF输入信号（2）转换为数字信号（9）的模拟数字转换器（8）; 数字信号处理单元（10）数字处理数字信号（9）; 将经处理的数字信号（13）转换成对应于RF输入信号（2）的环通RF信号（15）的数模转换器（14）; 以及输出环通RF信号（15）的环路输出（16）。
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