公开(公告)号：US20180113738A1

公开(公告)日：2018-04-26

申请号：US15497744

申请日：2017-04-26

Applicant: NETAPP, INC.

Inventor： Charles E. Nichols ,  Scott Terrill ,  Don Humlicek ,  Arindam Banerjee ,  Yulu Diao ,  Anthony D. Gitchell

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/5027

Abstract: A system for dynamically configuring and scheduling input/output (I/O) workloads among processing cores is disclosed. Resources for an application that are related to each other and/or not multicore safe are grouped together into work nodes. When these need to be executed, the work nodes are added to a global queue that is accessible by all of the processing cores. Any processing core that becomes available can pull and process the next available work node through to completion, so that the work associated with that work node software object is all completed by the same core, without requiring additional protections for resources that are not multicore safe. Indexes track the location of both the next work node in the global queue for processing and the next location in the global queue for new work nodes to be added for subsequent processing.

公开(公告)号：US10826848B2

公开(公告)日：2020-11-03

申请号：US15497744

申请日：2017-04-26

Applicant: NETAPP, INC.

Inventor： Charles E. Nichols ,  Scott Terrill ,  Don Humlicek ,  Arindam Banerjee ,  Yulu Diao ,  Anthony D. Gitchell

IPC: G06F9/46 ,  H04L12/861 ,  G06F9/50 ,  G06F12/0842 ,  G06F9/48

Abstract: A system for dynamically configuring and scheduling input/output (I/O) workloads among processing cores is disclosed. Resources for an application that are related to each other and/or not multicore safe are grouped together into work nodes. When these need to be executed, the work nodes are added to a global queue that is accessible by all of the processing cores. Any processing core that becomes available can pull and process the next available work node through to completion, so that the work associated with that work node software object is all completed by the same core, without requiring additional protections for resources that are not multicore safe. Indexes track the location of both the next work node in the global queue for processing and the next location in the global queue for new work nodes to be added for subsequent processing.

公开(公告)号：US20170097887A1

公开(公告)日：2017-04-06

申请号：US14874186

申请日：2015-10-02

Applicant: NetApp, Inc.

Inventor： Brian McKean ,  Kevin Kidney ,  Don Humlicek

IPC: G06F12/08 ,  G06F11/14 ,  G06F12/12

CPC classification number: G06F12/0804 ,  G06F11/1076 ,  G06F11/1415 ,  G06F12/0868 ,  G06F12/12 ,  G06F12/122 ,  G06F12/126 ,  G06F2201/805 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1032 ,  G06F2212/286 ,  G06F2212/312 ,  G06F2212/604

Abstract: Systems and techniques for performing a data transaction are disclosed that provide improved cache performance by pinning recovery information in a controller cache. In some embodiments, a data transaction is received by a storage controller of a storage system. The storage controller determines whether the data transaction is directed to a data stripe classified as frequently accessed. Data associated with the data transaction and recovery information associated with the data transaction are cached in a cache of the storage controller. The recovery information is pinned in the cache based on the data transaction being directed to the data stripe that is classified as frequently accessed, and the data is flushed from the cache independently from the pinned recovery information.

公开(公告)号：US20170097886A1

公开(公告)日：2017-04-06

申请号：US14874157

申请日：2015-10-02

Applicant: NetApp, Inc.

Inventor： Arindam Banerjee ,  Don Humlicek ,  Scott Terrill

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0804 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/126 ,  G06F2212/604

Abstract: Systems and techniques for cache management are disclosed that provide improved cache performance by prioritizing particular storage stripes for cache flush operations. The systems and techniques may also leverage features of the storage devices to provide atomicity without the overhead of inter-controller mirroring. In some embodiments, the systems and techniques include a storage controller that stores data in a cache. The data is associated with one or more sectors of a storage stripe that is defined over plurality of storage devices. The storage controller identifies a locality of dirty sectors of the one or more sectors, classifies the storage stripe into a category based on the locality, provides a category ordering of the category relative to at least one other category, and flushes the storage stripe from the cache to the plurality of storage devices according to the category ordering.