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    Storage Controller Caching Using Symmetric Storage Class Memory Devices
    1.
    发明申请
    Storage Controller Caching Using Symmetric Storage Class Memory Devices 审中-公开

    公开(公告)号：US20180165194A1

    公开(公告)日：2018-06-14

    申请号：US15892038

    申请日：2018-02-08

    Applicant: NetApp, Inc.

    Inventor： Brian McKean ,  Gregory Friebus ,  Sandeep Kumar R. Ummadi ,  Pradeep Ganesan

    IPC: G06F12/0804 ,  G06F12/02 ,  G06F12/0868 ,  G06F3/06

    Abstract: Systems and techniques for performing a data transaction are disclosed that provide data redundancy using two or more cache devices. In some embodiments, a data transaction is received by a storage controller of a storage system from a host system. The storage controller caches data and/or metadata associated with the data transaction to at least two cache devices that are discrete from the storage controller. After caching, the storage controller provides a transaction completion response to the host system from which the transaction was received. In some examples, each of the at least two cache devices includes a storage class memory. In some examples, the storage controller caches metadata to the at least two cache devices and to a controller cache of the storage controller, while data is cached to the at least two cache devices without being cached in the controller cache.

    Storage Controller Caching Using Symmetric Storage Class Memory Devices
    2.
    发明申请
    Storage Controller Caching Using Symmetric Storage Class Memory Devices 有权
    存储控制器缓存使用对称存储类存储器件

    公开(公告)号：US20170046259A1

    公开(公告)日：2017-02-16

    申请号：US14826870

    申请日：2015-08-14

    Applicant: NetApp, Inc.

    Inventor： Brian McKean ,  Gregory Friebus ,  Sandeep Kumar R. Ummadi ,  Pradeep Ganesan

    IPC: G06F12/08

    CPC classification number: G06F12/0804 ,  G06F3/06 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0868 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/312 ,  G06F2212/608

    Abstract: Systems and techniques for performing a data transaction are disclosed that provide data redundancy using two or more cache devices. In some embodiments, a data transaction is received by a storage controller of a storage system from a host system. The storage controller caches data and/or metadata associated with the data transaction to at least two cache devices that are discrete from the storage controller. After caching, the storage controller provides a transaction completion response to the host system from which the transaction was received. In some examples, each of the at least two cache devices includes a storage class memory. In some examples, the storage controller caches metadata to the at least two cache devices and to a controller cache of the storage controller, while data is cached to the at least two cache devices without being cached in the controller cache.

    Abstract translation: 公开了用于执行数据事务的系统和技术，其使用两个或更多个高速缓存设备来提供数据冗余。 在一些实施例中，存储系统的存储控制器从主机系统接收数据事务。 存储控制器将与数据事务相关联的数据和/或元数据与存储控制器离散的至少两个缓存设备进行高速缓存。 缓存后，存储控制器向收到事务的主机系统提供事务完成响应。 在一些示例中，至少两个缓存设备中的每一个包括存储类存储器。 在一些示例中，存储控制器将元数据缓存到至少两个高速缓存设备和存储控制器的控制器高速缓存，而数据被缓存到至少两个高速缓存设备而不被缓存在控制器高速缓存中。

    Write Mirroring to Storage Class Memory Devices
    4.
    发明申请
    Write Mirroring to Storage Class Memory Devices 有权
    将镜像写入存储类存储器件

    公开(公告)号：US20170046268A1

    公开(公告)日：2017-02-16

    申请号：US14826703

    申请日：2015-08-14

    Applicant: NetApp, Inc.

    Inventor： Sandeep Kumar R. Ummadi ,  Brian McKean ,  Gregory Friebus ,  Pradeep Ganesan

    IPC: G06F12/08

    CPC classification number: G06F12/0875 ,  G06F3/06 ,  G06F3/0617 ,  G06F3/0619 ,  G06F11/00 ,  G06F11/14 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0802 ,  G06F2212/60

    Abstract: Systems and techniques are disclosed for the mirroring of cache data from a storage controller to a storage class memory (“SCM”) device. The storage controller receives a write request, caches the write data, and mirrors the write data to the SCM device instead of to a cache of another storage controller. The SCM device stores the mirrored data in the SCM device. The storage controller acknowledges the write to the host. If the storage controller later fails, an alternate controller assumes ownership of storage volumes associated with the failed controller. Upon receipt of a new read request to the failed controller, the alternate controller checks the SCM device for a cache hit. If there is, the data is read from the SCM device; otherwise, it is read from the storage volume(s). The read data is cached at the alternate controller and then sent on to the requesting host.

    Abstract translation: 公开了用于将高速缓存数据从存储控制器镜像到存储类存储器（“SCM”）设备的系统和技术。 存储控制器接收写入请求，缓存写入数据，并将写入数据镜像到SCM设备，而不是另一个存储控制器的缓存。 SCM设备将镜像数据存储在SCM设备中。 存储控制器确认写入主机。 如果存储控制器以后发生故障，备用控制器将承担与故障控制器关联的存储卷的所有权。 在接收到失败的控制器的新的读取请求后，备用控制器检查SCM设备以获得高速缓存命中。 如果存在，则从SCM设备读取数据; 否则，从存储卷读取它。 读取的数据在备用控制器缓存，然后发送到请求主机。

    Storage controller caching using symmetric storage class memory devices
    5.
    发明授权
    Storage controller caching using symmetric storage class memory devices 有权

    公开(公告)号：US10698818B2

    公开(公告)日：2020-06-30

    申请号：US15892038

    申请日：2018-02-08

    Applicant: NetApp, Inc.

    Inventor： Brian McKean ,  Gregory Friebus ,  Sandeep Kumar R. Ummadi ,  Pradeep Ganesan

    IPC: G06F12/00 ,  G06F12/0804 ,  G06F12/02 ,  G06F12/0868 ,  G06F3/06

    Abstract: Systems and techniques for performing a data transaction are disclosed that provide data redundancy using two or more cache devices. In some embodiments, a data transaction is received by a storage controller of a storage system from a host system. The storage controller caches data and/or metadata associated with the data transaction to at least two cache devices that are discrete from the storage controller. After caching, the storage controller provides a transaction completion response to the host system from which the transaction was received. In some examples, each of the at least two cache devices includes a storage class memory. In some examples, the storage controller caches metadata to the at least two cache devices and to a controller cache of the storage controller, while data is cached to the at least two cache devices without being cached in the controller cache.

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