公开(公告)号：US20230010660A1

公开(公告)日：2023-01-12

申请号：US17660446

申请日：2022-04-25

申请人： Netlist, Inc.

发明人： Hyun LEE

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/0815

摘要： A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals. The NV controller and the non-volatile memory can be mounted on the motherboard.

公开(公告)号：US20200334150A1

公开(公告)日：2020-10-22

申请号：US16835024

申请日：2020-03-30

申请人： Netlist, Inc.

发明人： Hyun LEE ,  Junkil RYU

IPC分类号： G06F12/0813 ,  G06F9/455 ,  G06F13/00 ,  H04L29/08 ,  G06F12/109 ,  G06F12/02 ,  G06F12/1045

摘要： The present application presents a Uniform Memory Access (UMA) network including a cluster of UMA nodes each having at least one UMA memory unit and a server local to the at least one UMA memory unit. A respective UMA memory unit in a respective UMA node comprises persistent memory; non-persistent memory, a node control device operatively coupled to the persistent memory and the non-persistent memory, a local interface for interfacing with the local server in the respective UMA node, and a network interface for interfacing with the UMA network. The node control device is configured to translate between a local unified memory access (UMA) address space accessible by applications running on the local server and a global UMA address space that is mapped to a physical UMA address space. The physical UMA address space includes physical address spaces associated with different UMA nodes in the cluster of UMA nodes. Thus, a server in the UMA network can access the physical address spaces at other UMA nodes without going through the servers in the other UMA nodes.

公开(公告)号：US20170212700A1

公开(公告)日：2017-07-27

申请号：US15255894

申请日：2016-09-02

申请人： NetList, Inc.

发明人： Hyun LEE

IPC分类号： G06F3/06 ,  G06F12/0815

CPC分类号： G06F3/0619 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0815 ,  G06F12/0868 ,  G06F2212/214 ,  G06F2212/621

摘要： A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals. The NV controller and the non-volatile memory can be mounted on the motherboard.

公开(公告)号：US20210173567A1

公开(公告)日：2021-06-10

申请号：US16932611

申请日：2020-07-17

申请人： Netlist, Inc.

发明人： Hyun LEE

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/0815

摘要： A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals. The NV controller and the non-volatile memory can be mounted on the motherboard.

公开(公告)号：US20240020024A1

公开(公告)日：2024-01-18

申请号：US18353597

申请日：2023-07-17

申请人： Netlist, Inc.

发明人： Hyun LEE

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/0815

CPC分类号： G06F3/0619 ,  G06F12/0246 ,  G06F12/0868 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/0685 ,  G06F12/0815 ,  G06F2212/214 ,  G06F2212/621

摘要： A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the nonvolatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals. The NV controller and the non-volatile memory can be mounted on the motherboard.

公开(公告)号：US20220179789A1

公开(公告)日：2022-06-09

申请号：US17522705

申请日：2021-11-09

申请人： Netlist, Inc.

发明人： Hyun LEE ,  Junkil RYU

IPC分类号： G06F12/0813 ,  G06F9/455 ,  G06F13/00 ,  H04L65/40 ,  G06F12/109 ,  G06F12/02 ,  G06F12/1045

摘要： The present application presents a Uniform Memory Access (UMA) network including a cluster of UMA nodes. A system in a UMA node comprises persistent memory; non-persistent memory, a node control device operatively coupled to the persistent memory and the non-persistent memory, a local interface for interfacing with the local server in the respective UMA node, and a network interface for interfacing with the UMA network. The node control device is configured to translate between a local unified memory access (UMA) address space accessible by applications running on a local server and a global UMA address space that is mapped to a physical UMA address space. The physical UMA address space includes physical address spaces associated with different UMA nodes in the cluster of UMA nodes. Thus, a server in the UMA network can access the physical address spaces at other UMA nodes without going through the servers in the other UMA nodes.

公开(公告)号：US20190079683A1

公开(公告)日：2019-03-14

申请号：US15976321

申请日：2018-05-10

申请人： Netlist, Inc.

发明人： Hyun LEE

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/0815

CPC分类号： G06F3/0619 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0815 ,  G06F12/0868 ,  G06F2212/214 ,  G06F2212/621

摘要： A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals. The NV controller and the non-volatile memory can be mounted on the motherboard.