公开(公告)号：US11561715B2

公开(公告)日：2023-01-24

申请号：US16950731

申请日：2020-11-17

申请人： Netlist, Inc.

发明人： Hyun Lee

IPC分类号： G06F3/06 ,  G06F13/10 ,  G06F12/02 ,  G06F13/28 ,  G06F12/06 ,  G06F12/0868

摘要： A memory module comprises a volatile memory subsystem, a non-volatile memory subsystem, and a module controller coupled to the volatile memory subsystem and to the non-volatile memory subsystem. The module controller is configurable to control data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller includes a data selection circuit configurable to pre-search data transferred from the non-volatile memory with respect to one or more search criteria before providing the pre-select data relevant to the one or more search criteria to the volatile memory subsystem.

公开(公告)号：US20230010660A1

公开(公告)日：2023-01-12

申请号：US17660446

申请日：2022-04-25

申请人： Netlist, Inc.

发明人： Hyun LEE

IPC分类号： G06F3/06 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/0815

摘要： A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals. The NV controller and the non-volatile memory can be mounted on the motherboard.

公开(公告)号：US11513725B2

公开(公告)日：2022-11-29

申请号：US17023302

申请日：2020-09-16

申请人： Netlist, Inc.

发明人： Jeekyoung Park ,  Jordan Horwich

IPC分类号： G06F3/06

摘要： A memory module according to some embodiments is operable in a computer system, and comprises a volatile memory subsystem and a module controller coupled to the volatile memory subsystem. The volatile memory subsystem is configurable to be coupled to a memory channel including a data bus, and includes dynamic random access memory (DRAM) devices. The memory module allows independent control of strobe paths and data paths between the DRAM devices and the data bus, and is configurable to perform a memory write operation during which write data is provided to the volatile memory subsystem together with write strobes transmitted via first strobe paths between the DRAM devices and the data bus, and a memory read operation during which read data from the volatile memory subsystem is output onto the data bus together with read strobes transmitted via second strobe paths between the module controller and the data bus.

公开(公告)号：US20220253380A1

公开(公告)日：2022-08-11

申请号：US17531743

申请日：2021-11-20

申请人： Netlist, Inc.

发明人： Hyun Lee ,  Jayesh R. Bhakta ,  Chi She Chen ,  Jeffery C. Solomon ,  Mario Jesus Martinez ,  Hao Le ,  Soon J. Choi

IPC分类号： G06F12/02 ,  G06F12/08 ,  G06F12/0871 ,  G06F3/06 ,  G11C7/10 ,  G06F13/28 ,  G06F13/10 ,  G06F12/06

摘要： A memory module comprises a volatile memory subsystem including DRAM, a non-volatile memory subsystem including Flash memory, and a module control device. The Flash memory includes main Flash providing a main Flash memory space and scratch Flash providing a scratch Flash memory space. The module control device is configured to receive a request from the memory controller to move one or more segments of data in a first Flash block in the main Flash to the DRAM and to, for each respective segment of data: select a respective set of pages in the DRAM; transfer respective data stored in the respective set of pages from the DRAM to a corresponding segment in the scratch Flash; and transfer the respective segment of data to the respective set of pages in the DRAM. Thus, data can be moved segment by segment between the DRAM and the Flash memory.

公开(公告)号：US11243886B2

公开(公告)日：2022-02-08

申请号：US16539895

申请日：2019-08-13

申请人： Netlist, Inc.

发明人： Hyun Lee ,  Jayesh R Bhakta ,  Chi She Chen ,  Jeffery C. Solomon ,  Mario Jesus Martinez ,  Hao Le ,  Soon J. Choi

IPC分类号： G06F12/0871 ,  G06F3/06 ,  G06F12/0897 ,  G06F13/28

摘要： A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.

公开(公告)号：US20210382834A1

公开(公告)日：2021-12-09

申请号：US17403832

申请日：2021-08-16

申请人： Netlist, Inc.

发明人： Jefferey C. Solomon ,  Jayesh R. Bhakta

IPC分类号： G06F13/16 ,  G11C5/04 ,  G06F13/00 ,  G06F12/00 ,  G06F13/42 ,  G11C7/10 ,  G11C15/00

摘要： A memory module operable to communicate data with a memory controller via a memory bus. The memory module comprises memory devices and logic configurable to receive and register a set of input address and control signals associated with a read or write memory command and to output data transfer control signals. The memory module further comprises circuitry coupled between the memory bus and the memory devices. The circuitry is configurable to be in any of a plurality of states including a first state and a second state, and to transition from the first state to the second state in response to the data transfer control signals. The circuitry in the first state is configured to disable signal communication through the circuitry. The circuitry in the second state is configured to transfer the data signals associated with the read or write command in accordance with a transfer time budget of the memory module.

公开(公告)号：US20210081138A1

公开(公告)日：2021-03-18

申请号：US17023302

申请日：2020-09-16

申请人： Netlist, Inc.

发明人： Jeekyoung Park ,  Jordan HORWICH

IPC分类号： G06F3/06

摘要： A memory module according to some embodiments is operable in a computer system, and comprises a volatile memory subsystem and a module controller coupled to the volatile memory subsystem. The volatile memory subsystem is configurable to be coupled to a memory channel including a data bus, and includes dynamic random access memory (DRAM) devices. The memory module allows independent control of strobe paths and data paths between the DRAM devices and the data bus, and is configurable to perform a memory write operation during which write data is provided to the volatile memory subsystem together with write strobes transmitted via first strobe paths between the DRAM devices and the data bus, and a memory read operation during which read data from the volatile memory subsystem is output onto the data bus together with read strobes transmitted via second strobe paths between the module controller and the data bus.

公开(公告)号：US10949339B2

公开(公告)日：2021-03-16

申请号：US15470856

申请日：2017-03-27

申请人： Netlist, Inc.

发明人： Hyun Lee ,  Jayesh R. Bhakta

IPC分类号： G06F12/00 ,  G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06

摘要： A memory module is configured to communicate with a memory controller. The memory module comprises DDR DRAM devices arranged in multiple ranks each of the same width as the memory module, and a module controller configured to receive and register input control signals for a read or write operation from the memory controller and to output registered address and control signals. The registered address and control signals selects one of the multiple ranks to perform the read or write operation. The module controller further outputs a set of module control signals in response to the input address and control signals. The memory module further comprises a plurality of byte-wise buffers controlled by the set of module control signals to actively drive respective byte-wise sections of each data signal associated with the read or write operation between the memory controller and the selected rank.

公开(公告)号：US10884923B2

公开(公告)日：2021-01-05

申请号：US16432700

申请日：2019-06-05

申请人： Netlist, Inc.

发明人： Hyun Lee ,  Jayesh R. Bhakta

IPC分类号： G06F12/0802 ,  G11C5/04 ,  G11C29/02 ,  G11C7/10

摘要： A memory module-includes memory device groups, and a control circuit configurable to receive a system clock and input address and control (C/A) signals from a memory controller, and output a module clock, module C/A signals and data buffer control signals. The memory module further includes data buffers corresponding to respective memory device groups and configurable to receive the module clock and the data buffer control signals from the control circuit. A respective data buffer includes a n-bit wide data path and logic configured to control the data path in response to the data buffer control signals. The n-bit wide data path includes at least one programmable delay element controlled by the logic. The respective data buffer is further configurable to generate a respective local clock having a respective programmable delay from the module clock and to provide the respective local clock to a respective memory device group.

公开(公告)号：US20200151123A1

公开(公告)日：2020-05-14

申请号：US16680060

申请日：2019-11-11

申请人： Netlist, Inc.

发明人： Hyun Lee

IPC分类号： G06F13/16 ,  G06F12/06 ,  G11C29/52 ,  G06F11/10 ,  G06F3/06 ,  G06F13/24 ,  G06F9/445 ,  G11C7/10 ,  G11C5/04

摘要： According to certain embodiments, a memory module is operable with a memory controller of a host system. The memory module includes a module controller configurable to receive address and control signals from the memory controller, and dynamic random access memory elements configurable to communicate data signals with the memory controller in accordance with the address and control signals. The module controller has an open-drain output and is configurable to drive the open-drain output with a first signal to indicate a parity error having occurred when the memory module is being accessed for a normal memory read or write operation. The module controller is further configurable to drive the open drain output with a second signal related to one or more training sequences when the memory module performs operations associated with the one or more training sequences and not associated with any normal memory read or write operations.