公开(公告)号：US09208844B1

公开(公告)日：2015-12-08

申请号：US14448841

申请日：2014-07-31

Applicant: Netronome Systems, Inc.

Inventor： Joseph M. Lamb ,  Chunli Cai ,  Ranjit D. Loboprabhu

IPC: H03K19/00 ,  G11C8/18 ,  G11C8/06

CPC classification number: G11C11/4093 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222

Abstract: An integrated circuit receives a DDR (Double Data Rate) data signal and an associated DDR clock signal, and communicates those signals from integrated circuit input terminals a substantial distance across the integrated circuit to a subcircuit that then receives and uses the DDR data. Within the integrated circuit, a DDR retiming circuit receives the DDR data signal and the associated DDR clock signal from the terminals. The DDR retiming circuit splits the DDR data signal into two components, and then transmits those two components over the substantial distance toward the subcircuit. The subcircuit then recombines the two components back into a single DDR data signal and supplies the DDR data signal and the DDR clock signal to the subcircuit. The DDR data signal and the DDR clock signal are supplied to the subcircuit in such a way that setup and hold time requirements of the subcircuit are met.

Abstract translation: 集成电路接收DDR（双倍数据速率）数据信号和相关联的DDR时钟信号，并将来自集成电路输入端的那些信号跨越集成电路传送到子电路，然后接收并使用DDR数据。 在集成电路中，DDR重定时电路从端子接收DDR数据信号和相关的DDR时钟信号。 DDR重定时电路将DDR数据信号分为两个部分，然后将这两个分量在相当大的距离上发送到子电路。 子电路然后将两个组件重新组合成单​​个DDR数据信号，并将DDR数据信号和DDR时钟信号提供给子电路。 DDR数据信号和DDR时钟信号以满足子电路的建立和保持时间要求的方式提供给子电路。