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公开(公告)号：US10586870B2
公开(公告)日：2020-03-10
申请号：US16116829
申请日：2018-08-29
发明人： Roda Kanawati , Paul D. Hurwitz
IPC分类号： H01L29/00 , H01L29/786 , H01L29/78 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/10 , H01L23/482
摘要： A structure includes channel regions located between source/drain regions, and a polysilicon gate structure including a plurality of gate fingers, each extending over a corresponding channel region. Each gate finger includes first and second rectangular portions extending in parallel with a first axis, and a connector portion that introduces an offset between the first and second rectangular portions along a second axis. This offset causes each source/drain region to have a first section with a first length along the second axis, and a second section with a second length along the second axis, greater than the first length. A single column of contacts having a first width along the second axis is provided in the first section of each source/drain region, and a single column of contacts having a second width along the second axis, greater than the first width, is provided in the second section of each source/drain region.
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公开(公告)号：US20180374842A1
公开(公告)日：2018-12-27
申请号：US16116816
申请日：2018-08-29
IPC分类号： H01L27/06 , H01L29/66 , H01L21/8238 , H01L21/761 , H01L21/762 , H01L21/8249 , H01L29/165 , H01L29/737 , H01L27/092 , H01L23/66 , H01L29/06 , H01L29/04
摘要： Methods and structures for improved isolation in a SiGe BiCMOS process or a CMOS process are provided. In one method, shallow trench isolation (STI) regions are formed in a first semiconductor region located over a semiconductor substrate. Dummy active regions of the first semiconductor region extend through the STI regions to an upper surface of the first semiconductor region. A grid of deep trench isolation (DTI) regions is also formed in the first semiconductor region, wherein the DTI regions extend entirely through the first semiconductor region. The grid of DTI regions includes a pattern that exhibits only T-shaped or Y-shaped intersections. The pattern defines a plurality of openings, wherein a dummy active region is located within each of the openings.
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公开(公告)号：US20180323114A1
公开(公告)日：2018-11-08
申请号：US15587969
申请日：2017-05-05
IPC分类号： H01L21/8238 , H01L27/092 , H01L21/762 , H01L21/266 , H01L29/06
CPC分类号： H01L21/823878 , H01L21/266 , H01L21/76224 , H01L21/823892 , H01L27/092 , H01L29/0646
摘要： Bulk CMOS RF switches having reduced parasitic capacitance are achieved by reducing the size and/or doping concentration of the switch's N-doped tap (N-Tap) element, which is used to conduct a bias voltage to a Deep N-Well disposed under each switch's P-Type body implant (P-Well). Both the P-Well and the N-Tap extend between an upper epitaxial silicon surface and an upper boundary of the Deep N-well. A low-doping-concentration approach utilizes intrinsic (lightly doped) N-type epitaxial material to provide a body region of the N-Tap element, whereby an N+ surface contact diffusion is separated from an underlying section of the Deep N-well by a region of intrinsic epitaxial silicon. An alternative reduced-size approach utilizes an open-ring deep trench isolation structure that surrounds the active switch region (e.g., the Deep N-well and P-Well), and includes a relatively small-sized N-Tap region formed in an open corner region of the isolation structure.
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公开(公告)号：US20190109055A1
公开(公告)日：2019-04-11
申请号：US16026006
申请日：2018-07-02
IPC分类号： H01L21/84 , H01L27/06 , H01L27/12 , H01L29/737 , H01L21/8249 , H01L29/66 , H01L29/165
摘要： A silicon-on-insulator (SOI) CMOS transistor and a SOI heterojunction bipolar transistor (HBT) are fabricated on the same semiconductor substrate. First and second SOI regions are formed over the semiconductor substrate. A SOI CMOS transistor is fabricated in the first SOI region, and a collector region of the SOI HBT is fabricated in the second SOI region. The collector region can be formed by performing a first implant to a local collector region in the second SOI region, and performing a second implant to an extrinsic collector region in the second SOI region, wherein the extrinsic collector region is separated from the local collector region. A SiGe base is formed over the collector region, wherein a dielectric structure separates portions of the SiGe region and the extrinsic collector region. The SOI CMOS transistor and SOI HBT may be used to implement a front end module of an RF system.
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公开(公告)号：US20180323757A1
公开(公告)日：2018-11-08
申请号：US16025996
申请日：2018-07-02
发明人： Paul D. Hurwitz , Roda Kanawati
摘要： An RF switch includes series-connected transistors having different threshold voltages, breakdown voltages and on-resistances, without relying on different channel lengths to provide these differences. A first set of transistors located near a power amplifier output are fabricated to have first channel regions with relatively high dopant concentrations. A second set of transistors located near an antenna input, are fabricated to have second channel regions with relatively low dopant concentrations. The first set of transistors can also include halo implants to increase the dopant concentrations in the first channel regions. Lightly doped drain (LDD) regions of the first set of transistors can have a lower dopant concentration (and be shallower) than LDD regions of the second set of transistors. Transistors in the first set have a relatively high on-resistance, a relatively high breakdown voltage and a relatively high threshold voltage, when compared with transistors in the second set.
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6.发明申请公开(公告)号：US20170338321A1
公开(公告)日：2017-11-23
申请号：US15158514
申请日：2016-05-18
发明人： Paul D. Hurwitz , Kurt Moen
IPC分类号： H01L29/45 , H03K17/687 , H01L29/786 , H01L29/66 , H01L29/417 , H01L21/285 , H01L29/40 , H01L27/12 , H01L21/768 , H01L21/3105 , H04B1/38 , H01L29/423
CPC分类号： H01L29/458 , H01L21/28518 , H01L21/2855 , H01L21/76843 , H01L27/1222 , H01L29/401 , H01L29/41733 , H01L29/42384 , H01L29/665 , H01L29/66772 , H01L29/78654 , H03K17/102 , H03K17/6872 , H03K17/693 , H04B1/38 , H04B1/48
摘要： A radio frequency (RF) switch includes a plurality of series-connected silicon-on-insulator (SOI) CMOS transistors fabricated using a 0.13 micron (or larger) process, wherein the SOI CMOS transistors include nickel silicide formed on the source/drain regions. Each of the series-connected SOI CMOS transistors has a gate length of about 0.13 microns or more, thereby enabling these SOI CMOS transistors to handle high power RF signals, and exhibit the high breakdown voltages required to implement an RF switch. The nickel silicide regions advantageously contribute to a relatively a low on-resistance (RON) of the SOI CMOS transistors, while consuming a relatively small amount of the underlying silicon regions during their fabrication. The SOI CMOS transistors can be fabricated on a relatively thin silicon layer, thereby contributing to a relatively low off capacitance (COFF) of the SOI CMOS transistors. As a result, an RON*COFF value of the RF switch is advantageously minimized.
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公开(公告)号：US20190109054A1
公开(公告)日：2019-04-11
申请号：US15727159
申请日：2017-10-06
IPC分类号： H01L21/84 , H01L29/66 , H01L21/8249 , H01L27/06 , H01L29/737 , H01L27/12 , H01L29/165
摘要： A silicon-on-insulator (SOI) CMOS transistor and a SOI heterojunction bipolar transistor (HBT) are fabricated on the same semiconductor substrate. First and second SOI regions are formed over the semiconductor substrate. A SOI CMOS transistor is fabricated in the first SOI region, and a collector region of the SOI HBT is fabricated in the second SOI region. The collector region can be formed by performing a first implant to a local collector region in the second SOI region, and performing a second implant to an extrinsic collector region in the second SOI region, wherein the extrinsic collector region is separated from the local collector region. A SiGe base is formed over the collector region, wherein a dielectric structure separates portions of the SiGe region and the extrinsic collector region. The SOI CMOS transistor and SOI HBT may be used to implement a front end module of an RF system.
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公开(公告)号：US20190089398A1
公开(公告)日：2019-03-21
申请号：US15709841
申请日：2017-09-20
发明人： Paul D. Hurwitz , Roda Kanawati
CPC分类号： H04B1/44 , H04B1/0475 , H04B15/02
摘要： A non-linear shunt circuit is coupled in a shunt-type configuration (e.g., parallel to an RF switch shunt branch) between a main signal line and ground in an RF circuit, and includes a harmonic cancellation element (HCE) (e.g., back-to-back diodes or diode-connected FETs) configured to cancel third harmonics generated on the main signal line by operation of an RF switch. The RF switch includes a series branch made up of multiple FETs coupled in series in the main signal line between a transmitter/receiver circuit and an antenna. The HCE is coupled to the main signal line either by way of a mid-point node or an input/output terminal of the RF switch's series branch. The non-linear shunt circuit also includes optional protection circuits that provide frequency-independent impedance through the HCE. Various techniques (e.g., active biasing) are optionally utilized to increase effectiveness to a wider range of the switch input power levels.
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公开(公告)号：US20180323187A1
公开(公告)日：2018-11-08
申请号：US15658252
申请日：2017-07-24
IPC分类号： H01L27/06 , H01L29/06 , H01L23/66 , H01L27/092 , H01L29/737 , H01L29/04 , H01L29/165 , H01L21/8249 , H01L21/762 , H01L21/761 , H01L21/8238 , H01L29/66
CPC分类号： H01L27/0623 , H01L21/761 , H01L21/76229 , H01L21/8238 , H01L21/8249 , H01L23/66 , H01L27/092 , H01L29/04 , H01L29/0646 , H01L29/0649 , H01L29/165 , H01L29/66242 , H01L29/7375
摘要： Methods and structures for improved isolation in a SiGe BiCMOS process or a CMOS process are provided. In one method, shallow trench isolation (STI) regions are formed in a first semiconductor region located over a semiconductor substrate. Dummy active regions of the first semiconductor region extend through the STI regions to an upper surface of the first semiconductor region. A grid of deep trench isolation (DTI) regions is also formed in the first semiconductor region, wherein the DTI regions extend entirely through the first semiconductor region. The grid of DTI regions includes a pattern that exhibits only T-shaped or Y-shaped intersections. The pattern defines a plurality of openings, wherein a dummy active region is located within each of the openings.
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公开(公告)号：US20180323115A1
公开(公告)日：2018-11-08
申请号：US15941234
申请日：2018-03-30
IPC分类号： H01L21/8238 , H01L29/06 , H01L21/266 , H01L27/092 , H01L21/762
CPC分类号： H01L21/823878 , H01L21/266 , H01L21/76224 , H01L21/823892 , H01L27/092 , H01L29/0646
摘要： Bulk CMOS RF switches having reduced parasitic capacitance are achieved by reducing the size and/or doping concentration of the switch's N-doped tap (N-Tap) element, which is used to conduct a bias voltage to a Deep N-Well disposed under each switch's P-Type body implant (P-Well). Both the P-Well and the N-Tap extend between an upper epitaxial silicon surface and an upper boundary of the Deep N-well. A low-doping-concentration approach utilizes intrinsic (lightly doped) N-type epitaxial material to provide a body region of the N-Tap element, whereby an N+ surface contact diffusion is separated from an underlying section of the Deep N-well by a region of intrinsic epitaxial silicon. An alternative reduced-size approach utilizes an open-ring deep trench isolation structure that surrounds the active switch region (e.g., the Deep N-well and P-Well), and includes a relatively small-sized N-Tap region formed in an open corner region of the isolation structure.
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