公开(公告)号：US06654909B1

公开(公告)日：2003-11-25

申请号：US09608959

申请日：2000-06-30

申请人： Nhon T. Quach ,  John H. Crawford ,  Chakravarthy Kosaraju ,  Venkatesh Nagapudi

发明人： Nhon T. Quach ,  John H. Crawford ,  Chakravarthy Kosaraju ,  Venkatesh Nagapudi

IPC分类号： G06F1100

CPC分类号： G06F11/073 ,  G06F11/0751 ,  G06F11/1064 ,  G06F12/1036

摘要： The invention relates to the design of highly reliable microprocessors and more specifically to the use of a dedicated state machine that periodically checks the validity of critical processor resources. In an embodiment of the present invention, an apparatus to detect errors in information stored in a processor resource includes an error detection component, which is configured to control the detection of errors in the information stored in the processor resource; and a comparison component coupled to the error detection component, which is configured to receive the information from the processor resource and inputs from the detection component. The comparison component is further configured to determine if the information is valid, and to output a signal to replace the information if the information if invalid.

摘要翻译： 本发明涉及高度可靠的微处理器的设计，更具体地涉及使用周期性地检查关键处理器资源的有效性的专用状态机。 在本发明的实施例中，检测存储在处理器资源中的信息中的错误的装置包括：错误检测部件，被配置为控制对存储在处理器资源中的信息中的错误的检测; 以及耦合到所述错误检测组件的比较组件，其被配置为从所述处理器资源接收所述信息并从所述检测组件输入。 所述比较部件还被配置为确定所述信息是否有效，并且如果所述信息是无效的，则输出信号以替换所述信息。

公开(公告)号：US07383468B2

公开(公告)日：2008-06-03

申请号：US10634899

申请日：2003-08-06

申请人： Nhon T. Quach ,  John H. Crawford ,  Chakravarthy Kosaraju ,  Venkatesh Nagapudi

发明人： Nhon T. Quach ,  John H. Crawford ,  Chakravarthy Kosaraju ,  Venkatesh Nagapudi

IPC分类号： G06F11/00

CPC分类号： G06F11/073 ,  G06F11/0751 ,  G06F11/1064 ,  G06F12/1036

摘要： The invention relates to the design of highly reliable microprocessors and more specifically to the use of a dedicated state machine that periodically checks the validity of critical processor resources. In an embodiment of the present invention, an apparatus to detect errors in information stored in a processor resource includes an error detection component, which is configured to control the detection of errors in the information stored in the processor resource; and a comparison component coupled to the error detection component, which is configured to receive the information from the processor resource and inputs from the detection component. The comparison component is further configured to determine if the information is valid, and to output a signal to replace the information if the information if invalid.

摘要翻译： 本发明涉及高度可靠的微处理器的设计，更具体地涉及使用周期性地检查关键处理器资源的有效性的专用状态机。 在本发明的实施例中，检测存储在处理器资源中的信息中的错误的装置包括：错误检测部件，被配置为控制对存储在处理器资源中的信息中的错误的检测; 以及耦合到所述错误检测组件的比较组件，其被配置为从所述处理器资源接收所述信息并从所述检测组件输入。 所述比较部件还被配置为确定所述信息是否有效，并且如果所述信息是无效的，则输出信号以替换所述信息。

公开(公告)号：US06510506B2

公开(公告)日：2003-01-21

申请号：US09752584

申请日：2000-12-28

申请人： Venkatesh Nagapudi ,  Chakravarthy Kosaraju

发明人： Venkatesh Nagapudi ,  Chakravarthy Kosaraju

IPC分类号： G06F1210

CPC分类号： G06F11/0763 ,  G06F12/0802

摘要： An embodiment of the present invention includes a tag array, a valid vector, and a detector. The tag array stores N tag entries. Each of the N tag entries contains a one-hot tag having K bits. Each of the K bits of the one-hot tag corresponds to a translation look-aside buffer (TLB) entry in a TLB array having K TLB entries. The valid vector stores N valid entries corresponding to the N tag entries. The detector detects an error when a tag entry is read out upon a fetch read operation.

公开(公告)号：US20050021897A1

公开(公告)日：2005-01-27

申请号：US10918586

申请日：2004-08-13

申请人： Chakravarthy Kosaraju

发明人： Chakravarthy Kosaraju

IPC分类号： G06F9/00 ,  G06F13/40 ,  H04L12/56 ,  G06F13/00

CPC分类号： H04L47/25 ,  G06F13/4072

摘要： The invention generally relates to a method, apparatus, and system to change one or more communication pathways in a processor without changing a physical component layout in the processor. For example, in an embodiment, the invention generally relates to a routing agent to change one or more communication pathways in a processor without changing the physical component layout in the processor. In an embodiment, the invention generally relates to the following method. The method comprises sending a control signal to one or more components within a processor to change one or more communication pathways in the processor without changing the physical component layout in the processor. In an embodiment, the invention generally relates to a method of changing the bandwidth between a processor and a device exterior to the processor without changing the physical component layout in the processor.

公开(公告)号：US06904502B2

公开(公告)日：2005-06-07

申请号：US10743069

申请日：2003-12-23

申请人： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

发明人： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/16 ,  G11C7/24

CPC分类号： G06F12/0891

摘要： The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs using a blind invalidate circuit in high-speed memories. In accordance with an embodiment of the present invention, a tag array memory circuit including a plurality of memory bit circuits coupled together to form an n-bit memory cell; and a blind invalidate circuit coupled to a memory bit circuit in the n-bit memory cell, the blind invalidate circuit to clear a bit in the memory bit circuit, if a primary clear bit line is asserted and a received bit value of a right-adjacent memory bit circuit is zero.

摘要翻译： 本发明涉及高可靠性高性能微处理器的设计，更具体地涉及在高速存储器中使用盲目无效电路的设计。 根据本发明的实施例，一种标签阵列存储电路，包括耦合在一起以形成n位存储单元的多个存储器位电路; 以及与n位存储器单元中的存储器位电路耦合的盲目无效电路，盲目无效电路清除存储器位电路中的一位，如果主清零位线被断言，并且接收到的位值为右， 相邻的存储器位电路为零。

公开(公告)号：US06826645B2

公开(公告)日：2004-11-30

申请号：US09737648

申请日：2000-12-13

申请人： Chakravarthy Kosaraju

发明人： Chakravarthy Kosaraju

IPC分类号： G06F1340

CPC分类号： G06F13/36

摘要： A method and apparatus in which an arbiter links to a processor having a flexible architecture, and the processor connects to a device through a point to point bus.

摘要翻译： 一种方法和装置，其中仲裁器链接到具有灵活架构的处理器，并且处理器通过点对点总线连接到设备。

公开(公告)号：US06775746B2

公开(公告)日：2004-08-10

申请号：US10435386

申请日：2003-05-12

申请人： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

发明人： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC分类号： G06F1210

CPC分类号： G06F12/0891

摘要： The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory circuit includes a plurality of memory bit circuits coupled together to form an n-bit memory cell, and a valid bit circuit coupled to the n-bit memory cell, the valid bit circuit being configured to be accessed simultaneously with the plurality of memory bit circuits.

公开(公告)号：US06907490B2

公开(公告)日：2005-06-14

申请号：US09738913

申请日：2000-12-13

申请人： Chakravarthy Kosaraju

发明人： Chakravarthy Kosaraju

IPC分类号： G06F9/00 ,  G06F13/40 ,  H04L12/56 ,  G06F3/00 ,  G06F13/42 ,  H04L12/66

CPC分类号： H04L47/25 ,  G06F13/4072

摘要： The invention generally relates to a method, apparatus, and system to change one or more communication pathways in a processor without changing a physical component layout in the processor. For example, in an embodiment, the invention generally relates to a routing agent to change one or more communication pathways in a processor without changing the physical component layout in the processor. In an embodiment, the invention generally relates to the following method. The method comprises sending a control signal to one or more components within a processor to change one or more communication pathways in the processor without changing the physical component layout in the processor. In an embodiment, the invention generally relates to a method of changing the bandwidth between a processor and a device exterior to the processor without changing the physical component layout in the processor.

摘要翻译： 本发明一般涉及一种改变处理器中的一个或多个通信路径而不改变处理器中的物理组件布局的方法，装置和系统。 例如，在一个实施例中，本发明一般涉及一种在不改变处理器内的物理组件布局的情况下改变处理器中的一个或多个通信路径的路由代理。 在一个实施例中，本发明一般涉及以下方法。 该方法包括向处理器内的一个或多个组件发送控制信号以改变处理器中的一个或多个通信路径，而不改变处理器中的物理组件布局。 在一个实施例中，本发明一般涉及一种在处理器外部改变处理器和设备之外的带宽的方法，而不改变处理器中的物理组件布局。

公开(公告)号：US06839814B2

公开(公告)日：2005-01-04

申请号：US10726492

申请日：2003-12-04

申请人： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

发明人： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0891

摘要： The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.

摘要翻译： 本发明涉及高度可靠的高性能微处理器的设计，更具体地说涉及使用高速缓存存储器保护方案（例如，1加热有效位方案和2热向量高速缓存方案）的设计。 这些保护方案保护缓存中标签阵列中使用的1-hot向量，并设计为提供硬件节省，以更高的速度运行并且易于实现。 根据本发明的一个实施例，一种标签阵列存储器，包括一个输入转换电路，用于接收1个热矢量，并将该1个热矢量转换为2个热矢量。 标签阵列存储器还包括耦合到输入转换电路的存储器阵列，存储器阵列以存储2-热矢量; 以及耦合到存储器阵列的输出转换电路，所述输出转换电路接收所述2-热矢量并将所述2-热矢量转换回所述1-热矢量。

公开(公告)号：US06675266B2

公开(公告)日：2004-01-06

申请号：US09750094

申请日：2000-12-29

申请人： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

发明人： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC分类号： G06F1200

CPC分类号： G06F12/0891

摘要： The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory circuit includes a plurality of memory bit circuits coupled together to form an n-bit memory cell, and a valid bit circuit coupled to the n-bit memory cell, the valid bit circuit being configured to be accessed simultaneously with the plurality of memory bit circuits.

摘要翻译： 本发明涉及高度可靠的高性能微处理器的设计，更具体地说涉及使用高速缓存存储器保护方案（例如，1加热有效位方案和2热向量高速缓存方案）的设计。 这些保护方案保护缓存中标签阵列中使用的1-hot向量，并且被设计为提供硬件节省，以更高的速度运行并且易于实现。 根据本发明的实施例，标签阵列存储电路包括耦合在一起以形成n位存储单元的多个存储器位电路和耦合到n位存储单元的有效位电路，有效位 电路被配置为与多个存储器位电路同时访问。