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    Modular turbo decoder for expanded code word length
    2.
    发明授权
    Modular turbo decoder for expanded code word length 有权
    用于扩展码字长度的模块化turbo解码器

    公开(公告)号：US06594792B1

    公开(公告)日：2003-07-15

    申请号：US09561333

    申请日：2000-04-28

    申请人： Stephen Michael Hladik ,  Abdallah Mahmoud Itani ,  Nick Andrew Van Stralen ,  Robert Gideon Wodnicki ,  John Anderson Fergus Ross

    发明人： Stephen Michael Hladik ,  Abdallah Mahmoud Itani ,  Nick Andrew Van Stralen ,  Robert Gideon Wodnicki ,  John Anderson Fergus Ross

    IPC分类号： H03M1329

    CPC分类号： H03M13/3905 ,  H03M13/2957 ,  H03M13/3933 ,  H03M13/3972

    摘要： A turbo decoder system utilizing a MAP decoding algorithm has a predetermined number of turbo decoder modules for decoding segments of a turbo code component code word in parallel, thereby expanding the block-length and data-rate capability of the turbo decoder system. Input data samples are provided to an interleaver/de-interleaver module wherein they are divided into segments of predetermined size, each segment being provided to a respective turbo decoder module. The outputs of each turbo decoder module are a posteriori probabilities which are re-ordered in the interleaver/de-interleaver module, segmented, and provided back to the turbo decoders as a priori information-bit probabilities. For the case of a turbo code comprising two component codes, the a posteriori information-bit probabilities are re-ordered according to the interleaver definition at the end of odd-numbered half iterations, while at the end of even-numbered half iterations, they are re-ordered according to the de-interleaver definition. Decoding continues until the desired number of iterations have been performed. Data decisions are made on the final a posteriori bit probability estimates.

    摘要翻译： 利用MAP解码算法的turbo解码器系统具有预定数量的turbo解码器模块，用于并行地解码turbo码分量码字的段，从而扩展turbo解码器系统的块长度和数据速率能力。 将输入数据样本提供给交织器/解交织器模块，其中它们被划分成预定大小的段，每个段被提供给相应的turbo解码器模块。 每个turbo解码器模块的输出是在交织器/解交织器模块中重排序的后验概率，被分段并作为先验信息比特概率返回给turbo解码器。 对于包括两个分量代码的turbo码的情况，根据奇数半迭代结束时的交织器定义重新排序后验信息比特概率，而在偶数半迭代结束时，它们 根据解交织器定义重新排序。 解码继续，直到执行所需的迭代次数。 对最终的后验位概率估计作出数据决定。

    Turbo decoder with modified input for increased code word length and data rate
    3.
    发明授权
    Turbo decoder with modified input for increased code word length and data rate 有权
    Turbo解码器具有修改的输入，增加码字长度和数据速率

    公开(公告)号：US06715120B1

    公开(公告)日：2004-03-30

    申请号：US09561334

    申请日：2000-04-28

    申请人： Stephen Michael Hladik ,  Abdallah Mahmoud Itani ,  Nick Andrew Van Stralen ,  Robert Gideon Wodnicki ,  John Anderson Fergus Ross

    发明人： Stephen Michael Hladik ,  Abdallah Mahmoud Itani ,  Nick Andrew Van Stralen ,  Robert Gideon Wodnicki ,  John Anderson Fergus Ross

    IPC分类号： H03M1329

    CPC分类号： H03M13/3905 ,  H03M13/2957 ,  H03M13/3933 ,  H03M13/3972

    摘要： A turbo decoder system utilizing a MAP decoding algorithm has a predetermined number of turbo decoder modules for decoding segments of a turbo code component code word in parallel, thereby expanding the block-length and data rate capability of the turbo decoder. Upon completion of any half iteration of the MAP decoding algorithm, the a posteriori bit probability estimates are provided to an interleave/de-interleave-and-convert-data function block wherein they are re-ordered, segmented, used to modify the original received data samples, and provided back to the respective turbo decoder modules as input data samples for the systematic bits. Decoding continues in this manner until a predetermined number of half iterations is performed, and data decisions are made on the final a posteriori estimates.

    摘要翻译： 利用MAP解码算法的turbo解码器系统具有预定数量的turbo解码器模块，用于并行地解码turbo码分量码字的段，从而扩展turbo解码器的块长度和数据速率能力。 在完成MAP解码算法的任何半迭代之后，将后验比特概率估计提供给交织/解交织和转换数据功能块，其中它们被重新排序，分段，用于修改原始接收 数据样本，并提供给相应的turbo解码器模块作为系统比特的输入数据样本。 以这种方式继续解码直到执行预定数量的半迭代，并且对最后的后验估计进行数据判定。

    High-speed turbo decoder
    5.
    发明授权
    High-speed turbo decoder 有权
    高速turbo解码器

    公开(公告)号：US06304996B1

    公开(公告)日：2001-10-16

    申请号：US09263566

    申请日：1999-03-08

    申请人： Nick Andrew Van Stralen ,  John Anderson Fergus Ross ,  Stephen Michael Hladik ,  Abdallah Mahmoud Itani ,  Robert Gideon Wodnicki

    发明人： Nick Andrew Van Stralen ,  John Anderson Fergus Ross ,  Stephen Michael Hladik ,  Abdallah Mahmoud Itani ,  Robert Gideon Wodnicki

    IPC分类号： H03M1303

    CPC分类号： H03M13/3905 ,  H03M13/2957 ,  H03M13/3911 ,  H03M13/3922 ,  H03M13/3961 ,  H03M13/6561 ,  H03M13/6572 ,  H03M13/658 ,  H03M13/6583 ,  H03M13/6591

    摘要： A high-speed turbo decoder utilizes a MAP decoding algorithm and includes a streamlined construction of functional units, or blocks, amenable to ASIC implementation. A gamma block provides symbol-by-symbol a posteriori state transition probability estimates. Two gamma probability function values are provided via selection switches to the alpha and beta blocks for calculating the alpha and beta probability function values, i.e., performing the alpha and beta recursions, respectively, in parallel, thus significantly increasing decoding speed. A scaling circuit monitors the values of the alpha and beta probability functions and prescribes a scale factor such that all such values at a trellis level remain within the precision limits of the system. A sigma block determines the a posteriori state transition probabilities (sigma values) and uses the sigma values to provide soft-decision outputs of the turbo decoder.

    摘要翻译： 高速turbo解码器利用MAP解码算法，并且包括易于实施ASIC的功能单元或块的流线型结构。 伽马块提供逐符号的后验状态转换概率估计。 两个伽马概率函数值通过选择开关提供给α和β块用于计算α和β概率函数值，即分别执行α和β递归，从而显着增加解码速度。 缩放电路监视α和β概率函数的值，并规定了比例因子，使得网格级别上的所有这些值都保持在系统的精度限度内。 西格玛块确定后验状态转移概率（sigma值），并使用西格玛值来提供turbo解码器的软判决输出。

    Methods and apparatus for generating test vectors and validating ASIC designs
    7.
    发明授权
    Methods and apparatus for generating test vectors and validating ASIC designs 失效
    用于生成测试向量和验证ASIC设计的方法和设备

    公开(公告)号：US5920830A

    公开(公告)日：1999-07-06

    申请号：US890273

    申请日：1997-07-09

    申请人： William Thomas Hatfield ,  Abdallah Mahmoud Itani ,  William Macomber Leue

    发明人： William Thomas Hatfield ,  Abdallah Mahmoud Itani ,  William Macomber Leue

    IPC分类号： G01R31/3183 ,  G01R31/28 ,  G06F9/45 ,  G06F9/455

    CPC分类号： G01R31/318307

    摘要： Methods and apparatus for generating test vectors for use in testing ASIC designs at both the functional and circuit levels, and for comparing the results of functional level and circuit level tests, employ a set of software tools to facilitate generating test vectors and to compare results of simulation at the functional level with results of simulation at the synthesized circuit level. The software tool set includes a preprocessor program which reads source files and produces skeleton test vector files, a compiler program for compiling the test vector files, and an output comparison program for comparing functional level test results with circuit simulation level test results.

    摘要翻译： 用于在功能和电路级别测试ASIC设计中用于生成测试向量的方法和装置，以及用于比较功能级别和电路级测试的结果的方法和装置，采用一组软件工具来促进生成测试向量并比较 在模拟功能水平与仿真结果在合成电路水平。 软件工具集包括一个预处理程序，它读取源文件并生成框架测试向量文件，编译程序用于编译测试向量文件，以及一个输出比较程序，用于将功能级测试结果与电路仿真级别测试结果进行比较。