摘要:
A turbo decoder control comprises an address generator for addressing systematic data, parity data, and systematic likelihood ratios according to a pre-determined memory mapping. The systematic data samples are accessed in the order required by the MAP decoding algorithm such that interleaving and de-interleaving functions in the MAP decoding algorithm are performed in real-time, i.e., without delay. Such memory-mapping in combination with data handling functions (e.g., multiplexing and combinatorial logic) minimizes memory requirements for the turbo decoder and allows for use of programmable interleavers, variable block lengths, and multiple code rates.
摘要:
A turbo decoder system utilizing a MAP decoding algorithm has a predetermined number of turbo decoder modules for decoding segments of a turbo code component code word in parallel, thereby expanding the block-length and data-rate capability of the turbo decoder system. Input data samples are provided to an interleaver/de-interleaver module wherein they are divided into segments of predetermined size, each segment being provided to a respective turbo decoder module. The outputs of each turbo decoder module are a posteriori probabilities which are re-ordered in the interleaver/de-interleaver module, segmented, and provided back to the turbo decoders as a priori information-bit probabilities. For the case of a turbo code comprising two component codes, the a posteriori information-bit probabilities are re-ordered according to the interleaver definition at the end of odd-numbered half iterations, while at the end of even-numbered half iterations, they are re-ordered according to the de-interleaver definition. Decoding continues until the desired number of iterations have been performed. Data decisions are made on the final a posteriori bit probability estimates.
摘要:
A high-speed turbo decoder utilizes a MAP decoding algorithm and includes a streamlined construction of functional units, or blocks, amenable to ASIC implementation. A gamma block provides symbol-by-symbol a posteriori state transition probability estimates. Two gamma probability function values are provided via selection switches to the alpha and beta blocks for calculating the alpha and beta probability function values, i.e., performing the alpha and beta recursions, respectively, in parallel, thus significantly increasing decoding speed. A scaling circuit monitors the values of the alpha and beta probability functions and prescribes a scale factor such that all such values at a trellis level remain within the precision limits of the system. A sigma block determines the a posteriori state transition probabilities (sigma values) and uses the sigma values to provide soft-decision outputs of the turbo decoder.
摘要:
A turbo decoder control comprises an address generator for addressing systematic data, parity data, and systematic likelihood ratios according to a pre-determined memory mapping. The systematic data samples are accessed in the order required by the MAP decoding algorithm such that interleaving and de-interleaving functions in the MAP decoding algorithm are performed in real-time, i.e., without delay. Such memory-mapping in combination with data handling functions (e.g., multiplexing and combinatorial logic) minimizes memory requirements for the turbo decoder and allows for use of programmable interleavers, variable block lengths, and multiple code rates.
摘要:
A turbo decoder system utilizing a MAP decoding algorithm has a predetermined number of turbo decoder modules for decoding segments of a turbo code component code word in parallel, thereby expanding the block-length and data rate capability of the turbo decoder. Upon completion of any half iteration of the MAP decoding algorithm, the a posteriori bit probability estimates are provided to an interleave/de-interleave-and-convert-data function block wherein they are re-ordered, segmented, used to modify the original received data samples, and provided back to the respective turbo decoder modules as input data samples for the systematic bits. Decoding continues in this manner until a predetermined number of half iterations is performed, and data decisions are made on the final a posteriori estimates.
摘要:
An imaging system includes a programmable detector framing node controlling generation of radiation and controlling radioscopic image detection. Radioscopic image data is acquired and communicated independently of a host computer operating system. The detector framing node controls events in real time according to an event instruction sequence and communicates received radioscopic image data to host memory through a computer communication bus. Image data is received from a selected flat panel detector of a plurality of different flat panel detectors. The image data is selectively reordered according to parameters of the selected flat panel detector before communication to host memory.
摘要:
An image detector monitoring system includes a detector framing node and a host computer having at least one host processor and a host memory. The detector framing node acquires image data, buffers the acquired image data, and outputs the image data to the host memory according to a predetermined communication protocol. The host computer executes operations according to a non-real time operating system, and a host memory stores the image data received from the detector framing node. The detector framing node is controlled by executing a plurality of event instructions, which are stored in an event queue. Some event instructions control a radiation generation system, while others control communication with an image detection system or control the detector framing node itself. Each event instruction executed by the detector framing node includes a bit flag indicating whether the event is to be traced by the detector framing node. Traced events are stored as entries in a response log in host memory. Each response log entry includes a time stamp indicating a time of execution of the traced event.
摘要:
A real time imaging system includes a programmable detector framing node controlling generation of radiation and controlling radioscopic image detection. Radioscopic image data is acquired and communicated by the detector framing node independently of a host computer operating system. The detector framing node controls events in real time according to an event instruction sequence and communicates the received radioscopic image data to host memory through a computer communication bus. The image data is received from a selected flat panel detector of a plurality of different flat panel detectors. The detector framing node is programmable by way of a pair of JTAG loops. The JTAG loops receive programming instructions from the host computer and from a pair of JTAG ports.
摘要:
A real time data acquisition system includes a personal computer and a detector framing node cooperating to control generation of radiation and control radiographic detection. Data is acquired by a detector framing node and communicated independently of a non-real time operating system running on a host computer. The detector framing node controls events in real time according to an event instruction sequence and communicates received radioscopic data to a host memory. Data is received from a selected flat panel detector of a plurality of different flat panel detectors. The data is received as single frames or continuous frames before communication to the host memory.
摘要:
A detector framing node controls generation of radiation and radioscopic image detection Radioscopic image data is acquired and communicated independently of a host computer operating system. The detector framing node controls events in real time according to an event instruction sequence and receives the image data by way of an image detection interface into a memory unit. The image data is output from the memory unit to host memory of the host computer through a computer communication interface and under the control of a control unit. The detector framing node selects a flat panel detector from a plurality of different flat panel detectors and the image data is selectively reordered according to parameters of the selected flat panel detector before communication to host memory.