公开(公告)号：US5640583A

公开(公告)日：1997-06-17

申请号：US293981

申请日：1994-08-22

申请人： Nicolas C. Assouad ,  John P. Hill ,  David L. Dyer

发明人： Nicolas C. Assouad ,  John P. Hill ,  David L. Dyer

IPC分类号： G11B5/596 ,  G11B20/10 ,  G11B27/30 ,  G06F7/00

CPC分类号： G11B20/10 ,  G11B27/3027 ,  G11B5/59655 ,  G11B2020/1282

摘要： A disk drive controller integrated circuit includes a programmable servo burst decoder that can process any one of a plurality of servo sectors. A disk drive head reads each embedded servo sector on the disk and provides an analog signal, a servo burst, representing the servo sector to a preamp. The preamp provides an amplified analog signal to a read channel integrated circuit. The read channel integrated circuit provides input signals that are processed by the programmable servo burst decoder. The programmable servo burst decoder includes a programmable timing mark sequencer having an instruction register of a first size and a servo timing mark output line, and a programmable burst sequencer connected to the servo timing mark output line and having an instruction register of a second size. In this embodiment, the first size is different from the second size. Specifically, the first size is 20 bits, and the second size is 38 bits.

摘要翻译： 磁盘驱动器控制器集成电路包括可处理多个伺服扇区中的任一个的可编程伺服突发解码器。 磁盘驱动器头读取磁盘上的每个嵌入式伺服扇区，并将表示伺服扇区的模拟信号，伺服脉冲串提供给前置放大器。 前置放大器为读通道集成电路提供放大的模拟信号。 读通道集成电路提供由可编程伺服脉冲解码器处理的输入信号。 可编程伺服脉冲串解码器包括具有第一大小的指令寄存器和伺服定时标记输出线的可编程定时标记定序器和连接到伺服定时标记输出线并具有第二大小的指令寄存器的可编程脉冲序列发生器。 在该实施例中，第一尺寸与第二尺寸不同。 具体来说，第一大小是20比特，第二大小是38比特。

公开(公告)号：US5640538A

公开(公告)日：1997-06-17

申请号：US294128

申请日：1994-08-22

申请人： David L. Dyer ,  John P. Hill ,  Nicolas C. Assouad

发明人： David L. Dyer ,  John P. Hill ,  Nicolas C. Assouad

IPC分类号： G11B5/596 ,  G06F17/00

CPC分类号： G11B5/59616

摘要： A programmable timing mark sequencer automatically analyzes a sequence of data bits on a data input line. If the appropriate timing pattern is detected in the sequence of data bits, the timing mark sequencer drives a signal active on a servo timing mark output line. The timing mark sequencer is a fully programmable sequencer that is optimized for the detection of servo sector timing mark patterns. The timing mark sequencer includes a branch and fetch unit, a timing mark sequencer random access memory(RAM), an instruction register, a space counter, a window counter, and a synchronization flip-flop. The timing mark sequencer has a plurality of input lines including a search input line, a high resolution data bit line, and a decode clock line.

摘要翻译： 可编程定时标记定序器自动分析数据输入线上的数据位序列。 如果在数据位序列中检测到适当的定时模式，则定时标记定序器驱动在伺服定时标记输出线上有效的信号。 定时标记定序器是一个完全可编程的定序器，针对伺服扇区定时标记模式的检测进行了优化。 定时标记定序器包括分支和取出单元，定时标记定序器随机存取存储器（RAM），指令寄存器，空间计数器，窗口计数器和同步触发器。 定时标记定序器具有包括搜索输入线，高分辨率数据位线和解码时钟线的多条输入线。

公开(公告)号：US5826093A

公开(公告)日：1998-10-20

申请号：US363448

申请日：1994-12-22

申请人： Nicolas C. Assouad ,  David L. Dyer ,  Thomas G. Adams

发明人： Nicolas C. Assouad ,  David L. Dyer ,  Thomas G. Adams

IPC分类号： G06F3/06 ,  G06F15/78 ,  G06F15/00

CPC分类号： G06F3/0607 ,  G06F15/7814 ,  G06F3/0634 ,  G06F3/0658 ,  G06F3/0676

摘要： A single integrated circuit includes an on-board processor, a peripheral port, and a general purpose input/output (I/O) circuit that support both master mode and slave mode operations. In a master mode of operation, the integrated circuit functions as a disk drive microcontroller and seamlessly interfaces with a hard disk controller. The integrated circuit includes programmable circuitry for generating individual chip select signals for external random access memory (RAM) and external read-only memory (ROM); a fully programmable general purpose input/output interface; and a programmable bi-directional peripheral port. Each of these features are utilized in the master mode to control operation of the disk drive. In a slave mode of operation, the integrated circuit provides full motion control of the spin and tracking systems of a disk drive. In slave mode, the peripheral port is an interface to a host microcontroller or a host RISC processor, that is typically contained within the disk drive. The host microcontroller communicates with the integrated circuit through a set of mailbox registers within the peripheral port to configure the integrated circuit for full motion control and to receive information from the integrated circuit.

摘要翻译： 单个集成电路包括板载处理器，外围端口以及支持主模式和从模式操作的通用输入/输出（I / O）电路。 在主操作模式下，集成电路用作磁盘驱动器微控制器，并与硬盘控制器无缝连接。 集成电路包括用于产生用于外部随机存取存储器（RAM）和外部只读存储器（ROM）的单独芯片选择信号的可编程电路; 一个完全可编程的通用输入/输出接口; 和可编程双向外设端口。 这些特征中的每一个在主模式中被利用来控制磁盘驱动器的操作。 在从属操作模式下，集成电路为磁盘驱动器的自旋和跟踪系统提供全面的运动控制。 在从模式下，外设端口是主机微控制器或主机RISC处理器的接口，通常包含在磁盘驱动器中。 主机微控制器通过外围端口中的一组邮箱寄存器与集成电路进行通信，以配置集成电路进行全运动控制，并从集成电路接收信息。

公开(公告)号：US6119254A

公开(公告)日：2000-09-12

申请号：US997130

申请日：1997-12-23

申请人： Nicolas C. Assouad ,  David L. Dyer ,  Wen Lin

发明人： Nicolas C. Assouad ,  David L. Dyer ,  Wen Lin

IPC分类号： G01R31/28 ,  G06F11/26

CPC分类号： G06F11/261

摘要： A method of testing a processor controlled chip having embedded circuitry devoid of a direct connection external to said chip. Tracing circuitry embedded on the chip is programmed to detect the presence of specified information on a bus system embedded on the chip and devoid of a direct connection external to the chip. An address comparator detects the presence of the specified information on the bus system and opens gating circuitry in response to the detection. The specified information is extended through the gating circuitry and written in a buffer memory. The specified information can be read out of the buffer memory and extended to a user terminal external to the chip.

摘要翻译： 一种测试具有嵌入式电路的处理器控制芯片的方法，所述嵌入式电路在所述芯片外部没有直接连接。 嵌入在芯片上的跟踪电路被编程为检测嵌入在芯片上的总线系统上的指定信息的存在，并且没有芯片外部的直接连接。 地址比较器检测总线系统上的指定信息的存在，并响应于检测而打开门控电路。 指定的信息通过门控电路扩展并写入缓冲存储器。 指定的信息可以从缓冲存储器中读出并扩展到芯片外部的用户终端。

公开(公告)号：US06282501B1

公开(公告)日：2001-08-28

申请号：US09175586

申请日：1998-10-20

申请人： Nicolas C. Assouad

发明人： Nicolas C. Assouad

IPC分类号： G11B509

CPC分类号： G11B27/36 ,  G11B19/02 ,  G11B20/10527 ,  G11B2020/1062 ,  G11B2220/20

摘要： The invention includes a method and integrated circuit for testing a disk drive. The invention internally generates test inputs to the host interface in the disk drive. The test inputs emulate the actual inputs that a host computer would provide to the host interface. One version of the invention includes a drive control integrated circuit. The drive control integrated circuit comprises: a host interface, a processor, a buffer control, and compare circuitry. The processor processes test instructions to initiate a test pointer. The buffer control transfers commands from a buffer to the host interface in response to the pointer. The processor controls a write operation and a read operation in response to the commands. The compare circuitry compares the data block that is written to the address with another data block that is read from the address. The compare circuitry generates an alarm if the data blocks do not match.

摘要翻译： 本发明包括一种用于测试磁盘驱动器的方法和集成电路。 本发明在内部生成测试输入到磁盘驱动器中的主机接口。 测试输入模拟主机提供给主机接口的实际输入。 本发明的一个方案包括驱动控制集成电路。 驱动控制集成电路包括：主机接口，处理器，缓冲器控制和比较电路。 处理器处理测试指令以启动测试指针。 响应于指针，缓冲区控制将命令从缓冲区传送到主机接口。 处理器响应命令控制写操作和读操作。 比较电路将写入地址的数据块与从地址读取的另一个数据块进行比较。 如果数据块不匹配，比较电路会产生报警。

公开(公告)号：US4746997A

公开(公告)日：1988-05-24

申请号：US828211

申请日：1986-02-10

申请人： Louis J. Shrinkle ,  Nicolas C. Assouad

发明人： Louis J. Shrinkle ,  Nicolas C. Assouad

IPC分类号： G11B27/30 ,  G11B5/09

CPC分类号： G11B27/3027 ,  G11B2220/20

摘要： An address mark whose pattern is distinguishable from information data is produced by generating a number of relatively long pulses followed by a number of relatively shorter pulses. Preferably, a binary "1" is recirculated through a first predetermined number of stages of a shift register (for a first pre-established number of times) and then through a second (different) predetermined number of stages (for a second pre-established number of times). A signal level transition which defines the beginning or end of a pulse in the address mark pattern is generated in response to each binary "1" output from that shift register. The address mark pattern is detected by, preferably, supplying an input signal to be detected to the same aforementioned shift register, detecting n successive longer pulses and then detecting m successive shorter pulses, where n and m are less than the aforementioned first and second pre-established numbers, respectively. Pulse detection is obtained by sensing binary "0"s in each of successive stages of the shift register.

摘要翻译： 其图案与信息数据可区分的地址标记通过生成相对较长的脉冲数，然后产生相对较短的脉冲数来产生。 优选地，二进制“1”通过移位寄存器的第一预定数量级（对于第一预先确定的次数）再循环，然后通过第二（不同）预定数量的级（用于第二预先建立的 次数）。 响应于来自该移位寄存器的每个二进制“1”产生定义地址标记模式中的脉冲的开始或结束的信号电平转换。 地址标记图案通过优选地将待检测的输入信号提供给相同的上述移位寄存器来检测，检测n个连续较长的脉冲，然后检测m个连续的较短脉冲，其中n和m小于上述第一和第二预 - 建立数字。 通过在移位寄存器的每个连续级中检测二进制“0”来获得脉冲检测。

公开(公告)号：US5995308A

公开(公告)日：1999-11-30

申请号：US829218

申请日：1997-03-31

申请人： Nicolas C. Assouad ,  Thomas G. Adams ,  Aaron Wade Wilson

发明人： Nicolas C. Assouad ,  Thomas G. Adams ,  Aaron Wade Wilson

IPC分类号： G11B20/18 ,  G11B5/09

CPC分类号： G11B20/1883 ,  G11B2220/20

摘要： A disk resident system for managing defective data sector information in a defective data sector map in a headerless format magnetic disk device. The defective data sector map is stored in gaps between fields in the headerless disk format itself or in existing disk administration fields. The defective data sector map includes a plurality of binary digits that individually correspond to a defective or non-defective status of an individual data sector on at least one section of at least one track proximate to the defective data sector map. The defective data sector map can be minimized by compressing repetitive 0's or 1's in the map. ECC coding and/or other redundancy checks can be included to ensure validity of the defective data sector map.

摘要翻译： 一种用于在无头无格式磁盘装置中的缺陷数据扇区图中管理有缺陷的数据扇区信息的盘驻留系统。 有缺陷的数据扇区映射存储在无头磁盘格式本身或现有磁盘管理字段中的字段之间的间隙中。 有缺陷的数据扇区映射包括多个二进制数字，它们分别对应于邻近缺陷数据扇区映射的至少一个磁道的至少一个部分上的单个数据扇区的有缺陷或非缺陷状态。 可以通过压缩地图中的重复0或1来最小化缺陷数据扇区图。 可以包括ECC编码和/或其他冗余检查以确保有缺陷的数据扇区图的有效性。

公开(公告)号：US5963386A

公开(公告)日：1999-10-05

申请号：US829431

申请日：1997-03-31

申请人： Nicolas C. Assouad

发明人： Nicolas C. Assouad

IPC分类号： G11B5/012 ,  G11B20/12 ,  G11B20/18 ,  G11B5/09 ,  G11B5/596

CPC分类号： G11B20/18 ,  G11B20/1217 ,  G11B20/1258 ,  G11B2020/1234 ,  G11B2020/1284 ,  G11B5/012

摘要： A disk resident system for managing split data sector information in a headerless format magnetic disk device. The split data sector information is stored in a split data sector information field that is recorded in available areas within a headerless disk format such as the gaps within the headerless disk format or in available space within disk administration fields. Preferred areas within a headerless disk format include the gap immediate preceding a servo burst, the gap immediately following a servo burst, or within the servo burst itself, so that the split data sector information is readily available at the time the servo burst is read and interpreted. Information in a split data sector information field can include various combinations of the number of bytes in a split data sector segment that follows a first servo burst, the number of fixed length full data sectors between the first servo burst and an adjacent second servo burst, and the number of bytes in a split data sector segment that follows the second servo burst. Any split data sector information not expressly represented in a split data sector information field can be calculated because the number of bytes between a pair of adjacent servo bursts is known. Overlapping split data sector information in successive split data sector information fields can be used for look-ahead purposes or data integrity purposes. A split data sector information field can also be accompanied by an ECC type field for data integrity check purposes.

摘要翻译： 一种用于在无头格式磁盘装置中管理分割数据扇区信息的盘驻留系统。 分割数据扇区信息被存储在分割数据扇区信息字段中，该分割数据扇区信息字段被记录在无标题磁盘格式的可用区域内，例如无头无盘格式的间隙或磁盘管理字段内的可用空间中。 无头磁盘格式中的优选区域包括在伺服脉冲串之前的间隙，紧接着伺服脉冲串之后的间隙或者在伺服脉冲串本身之内的间隙，使得分割数据扇区信息在读取伺服脉冲串时容易获得; 解释 分割数据扇区信息字段中的信息可以包括在第一伺服脉冲串之后的分割数据扇区段中的字节数量，第一伺服脉冲串与相邻第二伺服脉冲串之间的固定长度全数据扇区的数量的各种组合， 以及在第二伺服脉冲串之后的分割数据扇区段中的字节数。 可以计算在分割数据扇区信息字段中未明确表示的任何分割数据扇区信息，因为一对相邻伺服脉冲串之间的字节数是已知的。 连续分割数据扇区信息字段中的重叠分割数据扇区信息可以用于预先目的或数据完整性目的。 分割数据扇区信息字段还可以伴随有用于数据完整性检查目的的ECC类型字段。

公开(公告)号：US06438715B1

公开(公告)日：2002-08-20

申请号：US09072514

申请日：1998-05-04

申请人： Nicolas C. Assouad

发明人： Nicolas C. Assouad

IPC分类号： H02H305

CPC分类号： G06F11/3485 ,  G11B19/02

摘要： The invention includes a drive control integrated circuit with an intelligent and efficient tracing capability. The drive control integrated circuit executes operating instructions grouped into modules. The drive control integrated circuit stores the module numbers for executed modules in a memory. System designers can then retrieve the module numbers from the memory to assess the operation of the drive control integrated circuit. Some typical modules are read, write, seek, error, and servo modules. The drive control integrated circuit also stores operating parameters associated with the executed modules in the memory. Some typical operating parameters are instruction codes, head numbers, cylinder numbers, and error codes. The invention allows system designers to specify a particular trace operation and wait for the drive control integrated circuit to load the module numbers and operational parameters of interest into the memory. The use of selected module numbers and operating parameters reduces the amount of data typically stored in conventional trace operation. The effect of the trace operation on system performance is negligible and allows for accurate system evaluation under realistic operating conditions.

摘要翻译： 本发明包括具有智能和高效跟踪能力的驱动控制集成电路。 驱动控制集成电路执行分组成模块的操作指令。 驱动控制集成电路将执行的模块的模块号存储在存储器中。 系统设计人员可以从内存中检索模块号，以评估驱动控制集成电路的运行情况。 一些典型的模块是读，写，寻找，错误和伺服模块。 驱动控制集成电路还将与执行的模块相关联的操作参数存储在存储器中。 一些典型的操作参数是指令代码，头数，柱面编号和错误代码。 本发明允许系统设计人员指定特定的跟踪操作，并等待驱动控制集成电路将感兴趣的模块编号和操作参数加载到存储器中。 使用选定的模块编号和操作参数减少了常规跟踪操作中典型存储的数据量。 跟踪操作对系统性能的影响可以忽略不计，可以在现实的操作条件下进行准确的系统评估。

公开(公告)号：US6084739A

公开(公告)日：2000-07-04

申请号：US829432

申请日：1997-03-31

申请人： Nicolas C. Assouad

发明人： Nicolas C. Assouad

IPC分类号： G11B5/012 ,  G11B19/06 ,  G11B19/247 ,  G11B20/10 ,  G11B20/12 ,  G11B27/30 ,  G11B5/596 ,  G11B5/09

CPC分类号： G11B20/10 ,  G11B19/06 ,  G11B19/247 ,  G11B20/1217 ,  G11B27/3027 ,  G11B2020/1287 ,  G11B2220/2516 ,  G11B5/012

摘要： A write synchronization system in a headerless format magnetic disk device. The system transmits encoded synchronization signals containing disk administration information such as servo burst information between a servo controller and other disk controller components such as a hard disk controller and a microprocessor or digital signal processor. The servo controller interprets the disk administration information read from the magnetic disk and sends an encoded signal to the other disk controller components for each servo burst encountered on when reading the disk. The disk administration information in the signals can be verified by comparing the contents of a present signal to the contents of at least one previous signal to determine if a servo burst from a sequence of servo bursts has been missed. A missing servo burst can also be identified by measuring the time interval between signals from the servo controller.

摘要翻译： 一种写头同步系统，以无头格式磁盘装置。 该系统在伺服控制器和诸如硬盘控制器和微处理器或数字信号处理器的其它盘控制器组件之间传送包含诸如伺服脉冲串信息之类的盘管理信息的编码同步信号。 伺服控制器解读从磁盘读取的磁盘管理信息，并在读取磁盘时遇到的每个伺服突发信号向其它磁盘控制器组件发送编码信号。 可以通过将当前信号的内容与至少一个先前信号的内容进行比较来确定信号中的盘管理信息，以确定是否错过了来自伺服脉冲序列的伺服脉冲串。 也可以通过测量来自伺服控制器的信号之间的时间间隔来识别丢失的伺服脉冲串。