Clock template for configuring a programmable gate array
    1.
    发明授权
    Clock template for configuring a programmable gate array 有权
    用于配置可编程门阵列的时钟模板

    公开(公告)号:US06732347B1

    公开(公告)日:2004-05-04

    申请号:US09844054

    申请日:2001-04-26

    IPC分类号: G06F1750

    CPC分类号: G06F1/10 G06F17/5054

    摘要: A clock template includes digital programming information for programming clock frames of a programmable gate array (PGA). The digital programming information represents a number of different clock configurations that correspond to various designs in the PGA. In one embodiment, the digital programming information includes a bit stream for partially reconfiguring the PGA. In another embodiment, the digital programming information is embedded in digital programming information of at least one of the designs. Methods of configuring a PGA with different designs having different clocking configurations by utilizing the clock template are also disclosed.

    摘要翻译: 时钟模板包括用于编程可编程门阵列(PGA)的时钟帧的数字编程信息。 数字编程信息表示与PGA中的各种设计相对应的多种不同的时钟配置。 在一个实施例中,数字节目信息包括用于部分重新配置PGA的比特流。 在另一个实施例中,数字节目信息被嵌入至少一个设计的数字节目信息中。 还公开了通过利用时钟模板来配置具有不同时钟配置的不同设计的PGA的方法。

    Run-time efficient methods for routing large multi-fanout nets
    2.
    发明授权
    Run-time efficient methods for routing large multi-fanout nets 有权
    运行时高效的路由大型多扇出网络的方法

    公开(公告)号:US08015535B1

    公开(公告)日:2011-09-06

    申请号:US12050447

    申请日:2008-03-18

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5077

    摘要: A method of limiting the routing resources of an integrated circuit (IC) that are available for use when routing multi-fanout nets can include selecting a multi-fanout net comprising a source and a plurality of loads and identifying each region of the IC which does not include at least one of the plurality of loads. Each of the regions can have a defined geometry. A type of routing resource can be selected which has a physical orientation with respect to the IC that corresponds to the geometry of the regions of the IC. Each routing resource of the selected type that is located within a region of the IC which does not include at least one of the plurality of loads can be excluded from consideration when routing the multi-fanout net.

    摘要翻译: 限制可用于路由多扇出网络的集成电路(IC)的路由资源的方法可以包括选择包括源和多个负载的多扇出网络,并且识别IC的每个区域 不包括多个负载中的至少一个。 每个区域可以具有限定的几何形状。 可以选择一种类型的路由资源,其具有相对于IC的物理取向,其对应于IC的区域的几何形状。 当路由多扇出网时,可以排除位于IC区域内不包括多个负载中的至少一个的所选类型的每个路由资源。

    Placing partitioned circuit designs within iterative implementation flows
    3.
    发明授权
    Placing partitioned circuit designs within iterative implementation flows 有权
    将分隔电路设计放在迭代实现流程中

    公开(公告)号:US07590960B1

    公开(公告)日:2009-09-15

    申请号:US11787925

    申请日:2007-04-18

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5054 G06F17/5072

    摘要: A method of placing circuit elements of a partitioned circuit design on a target programmable logic device (PLD) can include mapping circuit elements of the circuit design to corresponding partitions of the circuit design, selecting a circuit element of the circuit design, and selecting a candidate location within a logic boundary on the target PLD. The method also can include validating the candidate location for the selected circuit element, at least in part, according to whether the selected circuit element belongs to a same partition of the circuit design as at least one other circuit element already placed within the logic boundary. The selected circuit element can be selectively placed at the candidate location according to the validation.

    摘要翻译: 将分割电路设计的电路元件放置在目标可编程逻辑器件(PLD)上的方法可以包括将电路设计的电路元件映射到电路设计的相应分区,选择电路设计的电路元件,以及选择候选 位于目标PLD的逻辑边界内。 该方法还可以包括至少部分地根据所选择的电路元件是否属于与已经放置在逻辑边界内的至少一个其它电路元件的电路设计的相同分区来验证所选择的电路元件的候选位置。 所选择的电路元件可以根据验证选择性地放置在候选位置。

    Method and system for managing behavior of algorithms
    6.
    发明授权
    Method and system for managing behavior of algorithms 有权
    用于管理算法行为的方法和系统

    公开(公告)号:US07290241B1

    公开(公告)日:2007-10-30

    申请号:US10913752

    申请日:2004-08-06

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5054

    摘要: A method of managing behavior of algorithms includes specifying governing rules/policies that manage I-Set implementation directives, command line options, and environment variables and loading governing rules/policies into a behavior manager. Inside a client tool, the I-Set hierarchy processes and iterates one I-Set node at a time. Without more I-Sets to process, the method is done. If more, then the tool queries the Behavior Manager with an I-Set with symbolic designators of the queried behavior. The Behavior Manager can reply to the client tool indicating whether the queried behavior is to be supported on the appropriate logic of the I-Set node. If the algorithm for the I-Set node lacks the queried behavior, then another I-Set might require processing. If the algorithm for the I-Set node has the queried behavior, then the client tool applies the corresponding algorithm(s) on the appropriate logic.

    摘要翻译: 一种管理算法行为的方法包括指定管理I-Set实现指令,命令行选项和环境变量的管理规则/策略,并将管理规则/策略加载到行为管理器中。 在客户端工具中,I-Set层次结构一次处理并迭代一个I-Set节点。 没有更多的I-Sets要处理,该方法就完成了。 如果更多,那么该工具将使用具有查询行为的符号指示符的I-Set查询“行为管理器”。 行为管理器可以回复客户端工具,指示是否在I-Set节点的相应逻辑上支持查询行为。 如果I-Set节点的算法缺少查询行为,则另一个I-Set可能需要处理。 如果I-Set节点的算法具有查询行为,则客户端工具将相应的算法应用于适当的逻辑。

    Method of placement for iterative implementation flows
    7.
    发明授权
    Method of placement for iterative implementation flows 有权
    迭代实现流程的放置方法

    公开(公告)号:US07614025B1

    公开(公告)日:2009-11-03

    申请号:US11787785

    申请日:2007-04-18

    IPC分类号: G06F17/50 G06F9/45

    摘要: A method of implementing a circuit design in a target device can include identifying routing information for a circuit design that has been at least partially implemented. A plurality of empty sites of the target device within which the circuit design is to be implemented can be identified. The method also can include determining whether each of the plurality of empty sites of the target device has a routing conflict according to the routing information of the circuit design and generating a list specifying each empty site of the target device that has a routing conflict.

    摘要翻译: 在目标设备中实现电路设计的方法可以包括识别已经至少部分实现的电路设计的路由信息​​。 可以识别要实现电路设计的目标设备的多个空位。 该方法还可以包括根据电路设计的路由信息​​确定目标设备的多个空站点中的每一个是否具有路由冲突,并且生成指定具有路由冲突的目标设备的每个空站点的列表。

    Run-time efficient methods for routing large multi-fanout nets
    8.
    发明授权
    Run-time efficient methods for routing large multi-fanout nets 有权
    运行时高效的路由大型多扇出网络的方法

    公开(公告)号:US07376926B1

    公开(公告)日:2008-05-20

    申请号:US11119012

    申请日:2005-04-29

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5077

    摘要: A method of limiting the routing resources of an integrated circuit (IC) that are available for use when routing multi-fanout nets can include selecting a multi-fanout net comprising a source and a plurality of loads and identifying each region of the IC which does not include at least one of the plurality of loads. Each of the regions can have a defined geometry. A type of routing resource can be selected which has a physical orientation with respect to the IC that corresponds to the geometry of the regions of the IC. Each routing resource of the selected type that is located within a region of the IC which does not include at least one of the plurality of loads can be excluded from consideration when routing the multi-fanout net.

    摘要翻译: 限制可用于路由多扇出网络的集成电路(IC)的路由资源的方法可以包括选择包括源和多个负载的多扇出网络,并且识别IC的每个区域 不包括多个负载中的至少一个。 每个区域可以具有限定的几何形状。 可以选择一种类型的路由资源,其具有相对于IC的物理取向,其对应于IC的区域的几何形状。 当路由多扇出网时,可以排除位于IC区域内不包括多个负载中的至少一个的所选类型的每个路由资源。

    Implementation set-based guide engine and method of implementing a circuit design
    9.
    发明授权
    Implementation set-based guide engine and method of implementing a circuit design 有权
    实现集导向引擎和实现电路设计的方法

    公开(公告)号:US07171644B1

    公开(公告)日:2007-01-30

    申请号:US10912957

    申请日:2004-08-06

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5045

    摘要: A method of implementing an integrated circuit design can include the steps of forming a base implementation set and forming a guide implementation set having a plurality of guide implementation set nodes. The method can further include the steps of depositing directives on at least one guide implementation set node (or each node) among the plurality of guide implementation set nodes. The method can further include the steps of creating and depositing tasks on at least one guide implementation set node (or each node) among the plurality of guide implementation set nodes. The method can further include the steps of invoking each task deposited on guide implementation set nodes as each node in the guide implementation set tree is visited.

    摘要翻译: 实现集成电路设计的方法可以包括形成基本实现集合并形成具有多个指导实施集节点的指导实现集的步骤。 该方法还可以包括以下步骤:在多个指导实施集节点中的至少一个引导实施集节点(或每个节点)上存储指令。 该方法还可以包括以下步骤:在多个指导实施集节点中的至少一个指导实施集节点(或每个节点)上创建和存储任务。 该方法还可以包括在引导实现集树中的每个节点被访问时调用在指导实现集合节点上存储的每个任务的步骤。

    Method for computing and using future costing data in signal routing
    10.
    发明授权
    Method for computing and using future costing data in signal routing 失效
    在信号路由中计算和使用未来成本计算数据的方法

    公开(公告)号:US07073155B1

    公开(公告)日:2006-07-04

    申请号:US11019596

    申请日:2004-12-21

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5077

    摘要: A systematic method for calculating future cost is disclosed. Pre-routing is performed from a source node to other nodes through a series of neighboring nodes. At each node in the pre-routing, the cumulative routing cost and Manhattan distance are calculated. This cumulative routing cost is used as a new future cost for a specific distance if it is lower than or there is no existing future cost for that distance. A table can be used to store the future cost data. During routing, the recorded future cost is added to the cumulative cost of a node to help guide the routing, improving router run-time.

    摘要翻译: 披露了一种计算未来成本的系统方法。 通过一系列相邻节点从源节点到其他节点执行预路由。 在预路由中的每个节点处,计算累积路由成本和曼哈顿距离。 如果该累积路由成本低于或没有该距离的未来成本,则将其用作特定距离的新的未来成本。 可以使用表来存储未来的成本数据。 在路由期间,记录的未来成本将被添加到节点的累积成本,以帮助指导路由,从而改善路由器的运行时间。