公开(公告)号：US07080300B1

公开(公告)日：2006-07-18

申请号：US10777327

申请日：2004-02-12

申请人： Nigel G. Herron ,  Eric J. Thorne ,  Qingqi Wang ,  Anthony Correale, Jr. ,  Thomas Anderson Dick

发明人： Nigel G. Herron ,  Eric J. Thorne ,  Qingqi Wang ,  Anthony Correale, Jr. ,  Thomas Anderson Dick

IPC分类号： G01R31/28

CPC分类号： H03K19/17764 ,  G01R31/31717 ,  H03K19/17732

摘要： A circuit that includes a core device that is embedded within fixed interfacing logic circuitry that, in turn, is embedded in an FPGA fabric. The FPGA fabric may be configured into a test mode of operation to test either the embedded device or fixed logic devices formed within the fixed interfacing logic. While the FPGA is configured in a test mode, test circuitry and communication paths are made present within the fixed interfacing logic circuitry to facilitate the testing. Additionally, the test circuitry comprises isolation circuitry that is formed between various modules and circuits that are to be tested to isolate the device under test and to produce test signals thereto and there from during testing operations.

摘要翻译： 一种电路，其包括嵌入在固定接口逻辑电路中的核心器件，而固定接口逻辑电路又嵌入到FPGA架构中。 FPGA结构可以被配置成测试操作模式，以测试在固定接口逻辑中形成的嵌入式设备或固定逻辑设备。 当FPGA被配置在测试模式下时，测试电路和通信路径被存在于固定接口逻辑电路内以便于测试。 此外，测试电路包括形成在各种模块和电路之间的隔离电路，这些模块和电路将被测试以隔离被测器件，并在测试操作期间产生测试信号。

公开(公告)号：US06996758B1

公开(公告)日：2006-02-07

申请号：US09991410

申请日：2001-11-16

申请人： Nigel G. Herron ,  Eric J. Thorne ,  Qingqi Wang

发明人： Nigel G. Herron ,  Eric J. Thorne ,  Qingqi Wang

IPC分类号： G01R31/28

CPC分类号： H03K19/17764 ,  G01R31/31717 ,  H03K19/17732

摘要： A circuit that includes a core device that is embedded within fixed interfacing logic circuitry that, in turn, is embedded in an FPGA fabric. The FPGA fabric may be configured into a test mode of operation to test either the embedded device or fixed logic devices formed within the fixed interfacing logic. While the FPGA is configured in a test mode, test circuitry and communication paths are made present within the fixed interfacing logic circuitry to facilitate the testing. Additionally, the test circuitry comprises isolation circuitry that is formed between various modules and circuits that are to be tested to isolate the device under test and to produce test signals thereto and there from during testing operations.

摘要翻译： 一种电路，其包括嵌入在固定接口逻辑电路中的核心器件，而固定接口逻辑电路又嵌入在FPGA架构中。 FPGA结构可以被配置成测试操作模式，以测试在固定接口逻辑中形成的嵌入式设备或固定逻辑设备。 当FPGA被配置在测试模式下时，测试电路和通信路径被存在于固定接口逻辑电路内以便于测试。 此外，测试电路包括形成在各种模块和电路之间的隔离电路，这些模块和电路将被测试以隔离被测器件，并在测试操作期间产生测试信号。

公开(公告)号：US06983405B1

公开(公告)日：2006-01-03

申请号：US09991412

申请日：2001-11-16

申请人： Nigel G. Herron ,  Eric J. Thorne ,  Qingqi Wang

发明人： Nigel G. Herron ,  Eric J. Thorne ,  Qingqi Wang

IPC分类号： G01R31/28

CPC分类号： G01R31/318519 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17764

摘要： A circuit that includes a core device that is embedded within fixed interfacing logic circuitry that, in turn, is embedded in an FPGA fabric. The FPGA fabric may be configured into a test mode of operation to test either the embedded device or fixed logic devices formed within the fixed interfacing logic. While the FPGA is configured in a test mode, test circuitry and communication paths are made present within the fixed interfacing logic circuitry to facilitate the testing. Additionally, the test circuitry comprises isolation circuitry that is formed between various modules and circuits that are to be tested to isolate the device under test and to produce test signals thereto and therefrom during testing operations.

摘要翻译： 一种电路，其包括嵌入在固定接口逻辑电路中的核心器件，而固定接口逻辑电路又嵌入在FPGA架构中。 FPGA结构可以被配置成测试操作模式，以测试在固定接口逻辑中形成的嵌入式设备或固定逻辑设备。 当FPGA被配置在测试模式下时，测试电路和通信路径被存在于固定接口逻辑电路内以便于测试。 此外，测试电路包括形成在各个模块和电路之间的隔离电路，待测试的隔离被测设备并在测试操作期间产生测试信号。

公开(公告)号：US07117471B1

公开(公告)日：2006-10-03

申请号：US10971221

申请日：2004-10-22

申请人： Huimou Juliana Li ,  Mehul R. Vashi ,  Qingqi Wang ,  Andy H. Gan

发明人： Huimou Juliana Li ,  Mehul R. Vashi ,  Qingqi Wang ,  Andy H. Gan

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： Generation of consistent connection data for a first circuit embedded in a second circuit. In one approach, a master file is established with design data that includes for each pin in the embedded circuit, a hardware description language (HDL) pin name from an HDL description of the embedded circuit, a schematic pin name of the second circuit to which a corresponding pin in the embedded circuit is to connect, a signal direction associated with the pin, and a name of a clock to trigger a signal on the pin. A plurality of design views are generated from the master file. Each design view has a unique format relative to the other design views and includes for each pin in the embedded circuit design, at least the HDL pin name, the associated schematic pin name, and a signal direction associated with the pin.

摘要翻译： 生成嵌入在第二电路中的第一电路的一致的连接数据。 在一种方法中，建立一个主文件，其设计数据包括嵌入式电路中的每个引脚，来自嵌入式电路的HDL描述的硬件描述语言（HDL）引脚名称，第二电路的示意性引脚名称， 嵌入式电路中的相应引脚是连接，与引脚相关联的信号方向，以及一个时钟名称以触发引脚上的信号。 从主文件生成多个设计视图。 每个设计视图具有相对于其他设计视图的独特格式，包括嵌入式电路设计中的每个引脚，至少HDL引脚名称，相关联的原理图引脚名称和与引脚相关联的信号方向。