公开(公告)号：US07080300B1

公开(公告)日：2006-07-18

申请号：US10777327

申请日：2004-02-12

申请人： Nigel G. Herron ,  Eric J. Thorne ,  Qingqi Wang ,  Anthony Correale, Jr. ,  Thomas Anderson Dick

发明人： Nigel G. Herron ,  Eric J. Thorne ,  Qingqi Wang ,  Anthony Correale, Jr. ,  Thomas Anderson Dick

IPC分类号： G01R31/28

CPC分类号： H03K19/17764 ,  G01R31/31717 ,  H03K19/17732

摘要： A circuit that includes a core device that is embedded within fixed interfacing logic circuitry that, in turn, is embedded in an FPGA fabric. The FPGA fabric may be configured into a test mode of operation to test either the embedded device or fixed logic devices formed within the fixed interfacing logic. While the FPGA is configured in a test mode, test circuitry and communication paths are made present within the fixed interfacing logic circuitry to facilitate the testing. Additionally, the test circuitry comprises isolation circuitry that is formed between various modules and circuits that are to be tested to isolate the device under test and to produce test signals thereto and there from during testing operations.

摘要翻译： 一种电路，其包括嵌入在固定接口逻辑电路中的核心器件，而固定接口逻辑电路又嵌入到FPGA架构中。 FPGA结构可以被配置成测试操作模式，以测试在固定接口逻辑中形成的嵌入式设备或固定逻辑设备。 当FPGA被配置在测试模式下时，测试电路和通信路径被存在于固定接口逻辑电路内以便于测试。 此外，测试电路包括形成在各种模块和电路之间的隔离电路，这些模块和电路将被测试以隔离被测器件，并在测试操作期间产生测试信号。

公开(公告)号：US06996758B1

公开(公告)日：2006-02-07

申请号：US09991410

申请日：2001-11-16

申请人： Nigel G. Herron ,  Eric J. Thorne ,  Qingqi Wang

发明人： Nigel G. Herron ,  Eric J. Thorne ,  Qingqi Wang

IPC分类号： G01R31/28

CPC分类号： H03K19/17764 ,  G01R31/31717 ,  H03K19/17732

摘要： A circuit that includes a core device that is embedded within fixed interfacing logic circuitry that, in turn, is embedded in an FPGA fabric. The FPGA fabric may be configured into a test mode of operation to test either the embedded device or fixed logic devices formed within the fixed interfacing logic. While the FPGA is configured in a test mode, test circuitry and communication paths are made present within the fixed interfacing logic circuitry to facilitate the testing. Additionally, the test circuitry comprises isolation circuitry that is formed between various modules and circuits that are to be tested to isolate the device under test and to produce test signals thereto and there from during testing operations.

摘要翻译： 一种电路，其包括嵌入在固定接口逻辑电路中的核心器件，而固定接口逻辑电路又嵌入在FPGA架构中。 FPGA结构可以被配置成测试操作模式，以测试在固定接口逻辑中形成的嵌入式设备或固定逻辑设备。 当FPGA被配置在测试模式下时，测试电路和通信路径被存在于固定接口逻辑电路内以便于测试。 此外，测试电路包括形成在各种模块和电路之间的隔离电路，这些模块和电路将被测试以隔离被测器件，并在测试操作期间产生测试信号。

公开(公告)号：US06983405B1

公开(公告)日：2006-01-03

申请号：US09991412

申请日：2001-11-16

申请人： Nigel G. Herron ,  Eric J. Thorne ,  Qingqi Wang

发明人： Nigel G. Herron ,  Eric J. Thorne ,  Qingqi Wang

IPC分类号： G01R31/28

CPC分类号： G01R31/318519 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17764

摘要： A circuit that includes a core device that is embedded within fixed interfacing logic circuitry that, in turn, is embedded in an FPGA fabric. The FPGA fabric may be configured into a test mode of operation to test either the embedded device or fixed logic devices formed within the fixed interfacing logic. While the FPGA is configured in a test mode, test circuitry and communication paths are made present within the fixed interfacing logic circuitry to facilitate the testing. Additionally, the test circuitry comprises isolation circuitry that is formed between various modules and circuits that are to be tested to isolate the device under test and to produce test signals thereto and therefrom during testing operations.

摘要翻译： 一种电路，其包括嵌入在固定接口逻辑电路中的核心器件，而固定接口逻辑电路又嵌入在FPGA架构中。 FPGA结构可以被配置成测试操作模式，以测试在固定接口逻辑中形成的嵌入式设备或固定逻辑设备。 当FPGA被配置在测试模式下时，测试电路和通信路径被存在于固定接口逻辑电路内以便于测试。 此外，测试电路包括形成在各个模块和电路之间的隔离电路，待测试的隔离被测设备并在测试操作期间产生测试信号。

公开(公告)号：US06651238B1

公开(公告)日：2003-11-18

申请号：US09837380

申请日：2001-04-17

申请人： Robert W. Wells ,  Robert D. Patrie ,  Eric J. Thorne ,  Michael M. Matera

发明人： Robert W. Wells ,  Robert D. Patrie ,  Eric J. Thorne ,  Michael M. Matera

IPC分类号： G06F1750

CPC分类号： G01R31/318519 ,  G01R31/2853 ,  G01R31/318342

摘要： Fault coverage for the programmable interconnect of a programmable logic device (PLD) is provided. A user's design is modeled, thereby determining the programmable interconnect path in the device. The user's logic design is then modified, thereby facilitating the detection of faults. Specifically, any function generators in the PLD are implemented as predetermined logic gates, thereby forming a logic gate tree design. The synchronous elements in the user's design are preserved and transformed, if necessary, to provide controllability. Then, a vector can be exercised in the new design. A first readback of the PLD can be compared to a second readback of a fault-free model of the design.

摘要翻译： 提供了可编程逻辑器件（PLD）的可编程互连的故障覆盖。 用户的设计被建模，从而确定设备中的可编程互连路径。 然后修改用户的逻辑设计，从而有助于检测故障。 具体地说，PLD中的任何函数发生器被实现为预定的逻辑门，从而形成逻辑门树设计。 如果需要，用户设计中的同步元素将被保留和转换，以提供可控性。 然后，可以在新设计中行使矢量。 可以将PLD的第一次回读与设计的无故障模型的第二次回读进行比较。

公开(公告)号：US06594610B1

公开(公告)日：2003-07-15

申请号：US09853351

申请日：2001-05-11

申请人： Shahin Toutounchi ,  Anthony P. Calderone ,  Zhi-Min Ling ,  Robert D. Patrie ,  Eric J. Thorne ,  Robert W. Wells

发明人： Shahin Toutounchi ,  Anthony P. Calderone ,  Zhi-Min Ling ,  Robert D. Patrie ,  Eric J. Thorne ,  Robert W. Wells

IPC分类号： G06F1900

CPC分类号： G01R31/318519 ,  G01R31/318342

摘要： A new testing method uses a field programmable gate array to emulate faults, instead of using a separate computer to simulate faults. In one embodiment, a few (e.g., two or three) known good FPGAs are selected. A fault is introduced into the design of a FPGA configuration. The configuration is loaded into the FPGAs. A test vector is applied and the result is evaluated. If the result is different from that of a fault-free configuration, the fault is caught. One application of this method is to evaluate fault coverage. A fault model that can be used in the present invention is disclosed.

摘要翻译： 新的测试方法使用现场可编程门阵列来模拟故障，而不是使用单独的计算机来模拟故障。 在一个实施例中，选择几个（例如，两个或三个）已知的良好FPGA。 在FPGA配置的设计中引入了一个故障。 将配置加载到FPGA中。 应用测试向量并评估结果。 如果结果与无故障配置的结果不同，则会发现故障。 这种方法的一个应用是评估故障覆盖。 公开了可用于本发明的故障模型。