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    Apparatus for testing an interconnecting logic fabric
    1.
    发明授权
    Apparatus for testing an interconnecting logic fabric 有权
    用于测试互连逻辑结构的装置

    公开(公告)号：US06996758B1

    公开(公告)日：2006-02-07

    申请号：US09991410

    申请日：2001-11-16

    申请人： Nigel G. Herron ,  Eric J. Thorne ,  Qingqi Wang

    发明人： Nigel G. Herron ,  Eric J. Thorne ,  Qingqi Wang

    IPC分类号： G01R31/28

    CPC分类号： H03K19/17764 ,  G01R31/31717 ,  H03K19/17732

    摘要： A circuit that includes a core device that is embedded within fixed interfacing logic circuitry that, in turn, is embedded in an FPGA fabric. The FPGA fabric may be configured into a test mode of operation to test either the embedded device or fixed logic devices formed within the fixed interfacing logic. While the FPGA is configured in a test mode, test circuitry and communication paths are made present within the fixed interfacing logic circuitry to facilitate the testing. Additionally, the test circuitry comprises isolation circuitry that is formed between various modules and circuits that are to be tested to isolate the device under test and to produce test signals thereto and there from during testing operations.

    摘要翻译： 一种电路，其包括嵌入在固定接口逻辑电路中的核心器件，而固定接口逻辑电路又嵌入在FPGA架构中。 FPGA结构可以被配置成测试操作模式，以测试在固定接口逻辑中形成的嵌入式设备或固定逻辑设备。 当FPGA被配置在测试模式下时，测试电路和通信路径被存在于固定接口逻辑电路内以便于测试。 此外，测试电路包括形成在各种模块和电路之间的隔离电路，这些模块和电路将被测试以隔离被测器件，并在测试操作期间产生测试信号。

    Testing a programmable logic device with embedded fixed logic using a scan chain
    2.
    发明授权
    Testing a programmable logic device with embedded fixed logic using a scan chain 有权
    使用扫描链测试具有嵌入式固定逻辑的可编程逻辑器件

    公开(公告)号：US07080300B1

    公开(公告)日：2006-07-18

    申请号：US10777327

    申请日：2004-02-12

    申请人： Nigel G. Herron ,  Eric J. Thorne ,  Qingqi Wang ,  Anthony Correale, Jr. ,  Thomas Anderson Dick

    发明人： Nigel G. Herron ,  Eric J. Thorne ,  Qingqi Wang ,  Anthony Correale, Jr. ,  Thomas Anderson Dick

    IPC分类号： G01R31/28

    CPC分类号： H03K19/17764 ,  G01R31/31717 ,  H03K19/17732

    摘要： A circuit that includes a core device that is embedded within fixed interfacing logic circuitry that, in turn, is embedded in an FPGA fabric. The FPGA fabric may be configured into a test mode of operation to test either the embedded device or fixed logic devices formed within the fixed interfacing logic. While the FPGA is configured in a test mode, test circuitry and communication paths are made present within the fixed interfacing logic circuitry to facilitate the testing. Additionally, the test circuitry comprises isolation circuitry that is formed between various modules and circuits that are to be tested to isolate the device under test and to produce test signals thereto and there from during testing operations.

    摘要翻译： 一种电路，其包括嵌入在固定接口逻辑电路中的核心器件，而固定接口逻辑电路又嵌入到FPGA架构中。 FPGA结构可以被配置成测试操作模式，以测试在固定接口逻辑中形成的嵌入式设备或固定逻辑设备。 当FPGA被配置在测试模式下时，测试电路和通信路径被存在于固定接口逻辑电路内以便于测试。 此外，测试电路包括形成在各种模块和电路之间的隔离电路，这些模块和电路将被测试以隔离被测器件，并在测试操作期间产生测试信号。

    Method and apparatus for testing circuitry embedded within a field programmable gate array
    3.
    发明授权
    Method and apparatus for testing circuitry embedded within a field programmable gate array 有权
    用于测试嵌入在现场可编程门阵列内的电路的方法和装置

    公开(公告)号：US06983405B1

    公开(公告)日：2006-01-03

    申请号：US09991412

    申请日：2001-11-16

    申请人： Nigel G. Herron ,  Eric J. Thorne ,  Qingqi Wang

    发明人： Nigel G. Herron ,  Eric J. Thorne ,  Qingqi Wang

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318519 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17764

    摘要： A circuit that includes a core device that is embedded within fixed interfacing logic circuitry that, in turn, is embedded in an FPGA fabric. The FPGA fabric may be configured into a test mode of operation to test either the embedded device or fixed logic devices formed within the fixed interfacing logic. While the FPGA is configured in a test mode, test circuitry and communication paths are made present within the fixed interfacing logic circuitry to facilitate the testing. Additionally, the test circuitry comprises isolation circuitry that is formed between various modules and circuits that are to be tested to isolate the device under test and to produce test signals thereto and therefrom during testing operations.

    摘要翻译： 一种电路，其包括嵌入在固定接口逻辑电路中的核心器件，而固定接口逻辑电路又嵌入在FPGA架构中。 FPGA结构可以被配置成测试操作模式，以测试在固定接口逻辑中形成的嵌入式设备或固定逻辑设备。 当FPGA被配置在测试模式下时，测试电路和通信路径被存在于固定接口逻辑电路内以便于测试。 此外，测试电路包括形成在各个模块和电路之间的隔离电路，待测试的隔离被测设备并在测试操作期间产生测试信号。

    Providing fault coverage of interconnect in an FPGA
    4.
    发明授权
    Providing fault coverage of interconnect in an FPGA 失效
    提供FPGA中互连的故障覆盖

    公开(公告)号：US06651238B1

    公开(公告)日：2003-11-18

    申请号：US09837380

    申请日：2001-04-17

    申请人： Robert W. Wells ,  Robert D. Patrie ,  Eric J. Thorne ,  Michael M. Matera

    发明人： Robert W. Wells ,  Robert D. Patrie ,  Eric J. Thorne ,  Michael M. Matera

    IPC分类号： G06F1750

    CPC分类号： G01R31/318519 ,  G01R31/2853 ,  G01R31/318342

    摘要： Fault coverage for the programmable interconnect of a programmable logic device (PLD) is provided. A user's design is modeled, thereby determining the programmable interconnect path in the device. The user's logic design is then modified, thereby facilitating the detection of faults. Specifically, any function generators in the PLD are implemented as predetermined logic gates, thereby forming a logic gate tree design. The synchronous elements in the user's design are preserved and transformed, if necessary, to provide controllability. Then, a vector can be exercised in the new design. A first readback of the PLD can be compared to a second readback of a fault-free model of the design.

    摘要翻译： 提供了可编程逻辑器件（PLD）的可编程互连的故障覆盖。 用户的设计被建模，从而确定设备中的可编程互连路径。 然后修改用户的逻辑设计，从而有助于检测故障。 具体地说，PLD中的任何函数发生器被实现为预定的逻辑门，从而形成逻辑门树设计。 如果需要，用户设计中的同步元素将被保留和转换，以提供可控性。 然后，可以在新设计中行使矢量。 可以将PLD的第一次回读与设计的无故障模型的第二次回读进行比较。

    Test circuit for and method of identifying a defect in an integrated circuit
    5.
    发明授权
    Test circuit for and method of identifying a defect in an integrated circuit 有权
    用于识别集成电路中的缺陷的测试电路和方法

    公开(公告)号：US07227364B1

    公开(公告)日：2007-06-05

    申请号：US11016473

    申请日：2004-12-16

    申请人： Yuezhen Fan ,  David Mark ,  Eric J Thorne ,  Zhi-Min Ling

    发明人： Yuezhen Fan ,  David Mark ,  Eric J Thorne ,  Zhi-Min Ling

    IPC分类号： G01R31/28 ,  G01R31/26

    CPC分类号： G01R31/318516 ,  G01R31/31717 ,  G01R31/31855

    摘要： The embodiments of the present invention enable a new metal diagnosis pattern based on a production test pattern to quickly identify open and short circuits of metal lines which cannot be probed, such as the long lines of a programmable logic device, and to further isolates the fault location for physical failure analysis. According to one aspect of the invention, a circuit locally drives a plurality of metal long line segments to determine whether a defect in a line is a short circuit, or further to identify the location of an open circuit.

    摘要翻译： 本发明的实施例使得能够基于生产测试图案的新的金属诊断模式快速识别不能探测的金属线的开路和短路，例如可编程逻辑器件的长线，并进一步隔离故障 物理故障分析的位置。 根据本发明的一个方面，电路局部地驱动多个金属长线段以确定线路中的缺陷是短路还是进一步识别开路的位置。

    Fault emulation testing of programmable logic devices
    6.
    发明授权
    Fault emulation testing of programmable logic devices 失效
    可编程逻辑器件的故障仿真测试

    公开(公告)号：US06594610B1

    公开(公告)日：2003-07-15

    申请号：US09853351

    申请日：2001-05-11

    申请人： Shahin Toutounchi ,  Anthony P. Calderone ,  Zhi-Min Ling ,  Robert D. Patrie ,  Eric J. Thorne ,  Robert W. Wells

    发明人： Shahin Toutounchi ,  Anthony P. Calderone ,  Zhi-Min Ling ,  Robert D. Patrie ,  Eric J. Thorne ,  Robert W. Wells

    IPC分类号： G06F1900

    CPC分类号： G01R31/318519 ,  G01R31/318342

    摘要： A new testing method uses a field programmable gate array to emulate faults, instead of using a separate computer to simulate faults. In one embodiment, a few (e.g., two or three) known good FPGAs are selected. A fault is introduced into the design of a FPGA configuration. The configuration is loaded into the FPGAs. A test vector is applied and the result is evaluated. If the result is different from that of a fault-free configuration, the fault is caught. One application of this method is to evaluate fault coverage. A fault model that can be used in the present invention is disclosed.

    摘要翻译： 新的测试方法使用现场可编程门阵列来模拟故障，而不是使用单独的计算机来模拟故障。 在一个实施例中，选择几个（例如，两个或三个）已知的良好FPGA。 在FPGA配置的设计中引入了一个故障。 将配置加载到FPGA中。 应用测试向量并评估结果。 如果结果与无故障配置的结果不同，则会发现故障。 这种方法的一个应用是评估故障覆盖。 公开了可用于本发明的故障模型。

    Method for determining interconnect line performance within an integrated circuit
    7.
    发明授权
    Method for determining interconnect line performance within an integrated circuit 有权
    确定集成电路内互连线性能的方法

    公开(公告)号：US07373538B1

    公开(公告)日：2008-05-13

    申请号：US11147019

    申请日：2005-06-07

    申请人： Tarek Eldin ,  Himanshu J. Verma ,  Feng Wang ,  Eric J Thorne

    发明人： Tarek Eldin ,  Himanshu J. Verma ,  Feng Wang ,  Eric J Thorne

    IPC分类号： G06F1/12 ,  H04L5/00 ,  H04L7/00

    CPC分类号： G01R31/31937 ,  G01R31/31725

    摘要： A method for determining propagation delay differences for conductive lines of an integrated circuit is described. A first path is formed by coupling a first portion of conductive lines together. The first portion is associated with a first region of the integrated circuit. The first path is coupled in a ring oscillator, and a first delay is determined. A second path is formed by coupling a second portion of the conductive lines together. The second portion is the first portion except for at least a first conductive line in the first portion of the conductive lines being swapped for a second conductive line. The second conductive line is associated with a second region of the integrated circuit. The second path is coupled in the ring oscillator circuit. A second delay is determined, and an incremental difference between the first delay and the second delay may be determined.

    摘要翻译： 描述了一种用于确定集成电路的导线的传播延迟差的方法。 通过将导电线的第一部分耦合在一起而形成第一路径。 第一部分与集成电路的第一区域相关联。 第一路径耦合在环形振荡器中，并且确定第一延迟。 通过将导电线的第二部分耦合在一起而形成第二路径。 第二部分是第一部分，除了导电线的第一部分中的至少第一导电线被交换用于第二导电线之外。 第二导线与集成电路的第二区域相关联。 第二路径耦合在环形振荡器电路中。 确定第二延迟，并且可以确定第一延迟和第二延迟之间的增量差。