公开(公告)号：US6128208A

公开(公告)日：2000-10-03

申请号：US401185

申请日：1999-09-23

申请人： Niichi Itoh ,  Yasunobu Nakase ,  Tetsuya Watanabe ,  Chikayoshi Morishima

发明人： Niichi Itoh ,  Yasunobu Nakase ,  Tetsuya Watanabe ,  Chikayoshi Morishima

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  G11C5/02

CPC分类号： H01L27/10844 ,  H01L27/10897

摘要： Provided is a semiconductor memory having a layout structure in which a memory cell has excellent patterning controllability. A pattern of element components (active regions 10 to 15 and 21 to 23 and polysilicon regions 31 to 42) of a memory cell for one memory cell unit of a memory cell array region 1 is identical to that of a dummy cell of a peripheral dummy cell region 3, and both patterns present a line symmetrical relationship with respect to a boundary line BC1. In addition, a pattern of the memory cell for one memory cell unit of the memory cell array region 1 is identical to that of a dummy cell of a power wiring region 2, and both patterns present a line symmetrical relationship with respect to a boundary line BC2.

摘要翻译： 提供一种具有布局结构的半导体存储器，其中存储单元具有优异的图案化可控性。 存储单元阵列区域1的一个存储单元单元的存储单元的元件部件（有源区域10至15和21至23以及多晶硅区域31至42）的图案与外围虚拟元件的虚设单元相同 单元区域3，并且两个图案相对于边界线BC1呈现线对称关系。 此外，存储单元阵列区域1的一个存储单元单元的存储单元的图案与电力布线区域2的虚设单元的图案相同，并且两个图案相对于边界线呈现线对称关系 BC2。

公开(公告)号：US06201758B1

公开(公告)日：2001-03-13

申请号：US09499044

申请日：2000-02-07

申请人： Chikayoshi Morishima ,  Yasunobu Nakase ,  Tetsuya Watanabe ,  Niichi Itoh

发明人： Chikayoshi Morishima ,  Yasunobu Nakase ,  Tetsuya Watanabe ,  Niichi Itoh

IPC分类号： G11C800

CPC分类号： G11C11/419

摘要： A precharge circuit and a bit line load circuit are provided to a read bit line pair. The bit line load circuit continuously supplies a prescribed current to a read bit line. When data is written to one of memory cells selected in common by one read word line, the level of each read bit line will not be lowered to the level of the ground potential by the bit line load circuit if a read word line is activated, and therefore the loads of both discharge and charge operations by transistors in the memory cell are reduced.

摘要翻译： 向读位线对提供预充电电路和位线负载电路。 位线负载电路将规定的电流连续地提供给读位线。 当将数据写入一个读取字线共同选择的存储器单元之一时，如果读取的字线被激活，则每个读取位线的电平将不会被位线负载电路降低到地电位的电平， 因此减小存储单元中的晶体管的放电和充电操作的负载。

公开(公告)号：US06327166B1

公开(公告)日：2001-12-04

申请号：US09651322

申请日：2000-08-31

申请人： Niichi Itoh ,  Yasunobu Nakase ,  Tetsuya Watanabe ,  Chikayoshi Morishima

发明人： Niichi Itoh ,  Yasunobu Nakase ,  Tetsuya Watanabe ,  Chikayoshi Morishima

IPC分类号： G11C502

CPC分类号： H01L27/10844 ,  H01L27/10897

摘要： Provided is a semiconductor memory having a layout structure in which a memory cell has excellent patterning controllability. A pattern of element components (active regions 10 to 15 and 21 to 23 and polysilicon regions 31 to 42) of a memory cell for one memory cell unit of a memory cell array region 1 is identical to that of a dummy cell of a peripheral dummy cell region 3, and both patterns present a line symmetrical relationship with respect to a boundary line BC1. In addition, a pattern of the memory cell for one memory cell unit of the memory cell array region 1 is identical to that of a dummy cell of a power wiring region 2, and both patterns present a line symmetrical relationship with respect to a boundary line BC2.

摘要翻译： 提供一种具有布局结构的半导体存储器，其中存储单元具有优异的图案化可控性。 存储单元阵列区域1的一个存储单元单元的存储单元的元件部件（有源区域10至15和21至23以及多晶硅区域31至42）的图案与外围虚拟元件的虚设单元相同 单元区域3，并且两个图案相对于边界线BC1呈现线对称关系。 此外，存储单元阵列区域1的一个存储单元单元的存储单元的图案与电力布线区域2的虚设单元的图案相同，并且两个图案相对于边界线呈现线对称关系 BC2。

公开(公告)号：US07394115B2

公开(公告)日：2008-07-01

申请号：US11335532

申请日：2006-01-20

申请人： Niichi Itoh

发明人： Niichi Itoh

IPC分类号： H01L27/10

CPC分类号： G06F1/10

摘要： A clock signal transmission line in the semiconductor integrated circuit device includes a plurality of straight portions arranged side by side in a predetermined direction and a plurality of bent portions connecting the respective straight portions. At least two of a plurality of signal lines to which a clock signal is transmitted are connected to different straight portions. Consequently, a semiconductor integrated circuit device which can reduce a clock skew when transmitting a clock signal to a plurality of signal lines is provided.

摘要翻译： 半导体集成电路器件中的时钟信号传输线包括沿预定方向并排设置的多个直线部分和连接各直线部分的多个弯曲部分。 传输时钟信号的多条信号线中的至少两条连接到不同的直线部分。 因此，提供了一种半导体集成电路器件，其可以在将时钟信号发送到多条信号线时减少时钟偏移。

公开(公告)号：US06856170B2

公开(公告)日：2005-02-15

申请号：US10442090

申请日：2003-05-21

申请人： Niichi Itoh

发明人： Niichi Itoh

IPC分类号： G06F1/06 ,  H01L21/82 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H03K5/00 ,  H03K5/15 ,  H03K19/094

CPC分类号： H03K5/15 ,  G06F1/06 ,  H01L27/0207

摘要： A clock generator (10a) outputs either a first clock signal or a second clock signal. The second clock signal is higher in frequency than the first clock signal. Under control of a control signal (CNTL1), when the first clock signal and the second clock signal are outputted from the clock generator (10a), a selector (81a) transmits the first and second clock signals to a clock transmission line (42) and to a clock transmission line (41), respectively. The clock transmission line (41) is greater in linewidth than the clock transmission line (42). Under control of the control signal (CNTL1), a selector (82a) connects either the clock transmission line (41) or the clock transmission line (42) to the outside.

摘要翻译： 时钟发生器（10a）输出第一时钟信号或第二时钟信号。 第二时钟信号的频率高于第一时钟信号。 在控制信号（CNTL1）的控制下，当从时钟发生器（10a）输出第一时钟信号和第二时钟信号时，选择器（81a）将第一和第二时钟信号发送到时钟传输线（42） 和时钟传输线（41）。 时钟传输线（41）的线宽比时钟传输线（42）大。 在控制信号（CNTL1）的控制下，选择器（82a）将时钟传输线（41）或时钟传输线（42）连接到外部。

公开(公告)号：US20060123372A1

公开(公告)日：2006-06-08

申请号：US11335532

申请日：2006-01-20

申请人： Niichi Itoh

发明人： Niichi Itoh

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F1/10

摘要： A clock signal transmission line in the semiconductor integrated circuit device includes a plurality of straight portions arranged side by side in a predetermined direction and a plurality of bent portions connecting the respective straight portions. At least two of a plurality of signal lines to which a clock signal is transmitted are connected to different straight portions. Consequently, a semiconductor integrated circuit device which can reduce a clock skew when transmitting a clock signal to a plurality of signal lines is provided.

公开(公告)号：US07026667B2

公开(公告)日：2006-04-11

申请号：US10226204

申请日：2002-08-23

申请人： Niichi Itoh

发明人： Niichi Itoh

IPC分类号： H01L27/10

CPC分类号： G06F1/10

摘要： A clock signal transmission line in the semiconductor integrated circuit device includes a plurality of straight portions arranged side by side in a predetermined direction and a plurality of bent portions connecting the respective straight portions. At least two of a plurality of signal lines to which a clock signal is transmitted are connected to different straight portions. Consequently, a semiconductor integrated circuit device which can reduce a clock skew when transmitting a clock signal to a plurality of signal lines is provided.

公开(公告)号：US20050138102A1

公开(公告)日：2005-06-23

申请号：US10989413

申请日：2004-11-17

申请人： Niichi Itoh

发明人： Niichi Itoh

IPC分类号： G06F7/52 ,  G06F7/523 ,  G06F7/53 ,  G06F7/533

CPC分类号： G06F7/5318 ,  G06F7/5332

摘要： An arithmetic unit is provided which is capable of enhancing area efficiency while suppressing operating speed reduction. A third partial product adder (T101) is divided into a high order part (T101a) including high-order 12 bits and a low order part (T101b) including low-order 33 bits. The high order part (T101a) and the low order part (T101b) are placed in different rows in a Wallace tree array. Particularly, the low order part (T101b) is placed in a middle row in the Wallace tree array. More specifically, the low order part (T101b) is placed right under a high order part (S101a) and right above a low order part (S102b). The high order part (T101a) is placed in the bottom row of the Wallace tree array. More specifically, the high order part (T101a) is placed right under a high order part (S102a).

摘要翻译： 提供了一种能够在抑制运行速度降低的同时提高面积效率的运算单元。 第三部分乘积加法器（T101）被分成包括高阶12位的高阶部分（T 101a）和包括低阶33位的低阶部分（T 101b）。 在华莱士树阵列中，高阶部分（T 101 a）和低阶部分（T 101 b）被放置在不同的行中。 特别地，低阶部分（T 101b）被放置在Wallace树阵列的中间行中。 更具体地，低阶部分（T 101b）被放置在高阶部分（S101a）的正下方，并且位于低阶部分（S102b）的正上方。 高阶部分（T 101 a）被放置在华莱士树阵列的底行。 更具体地，高阶部分（T 101 a）被放置在高阶部分（S102a）的正下方。

公开(公告)号：US20050246407A1

公开(公告)日：2005-11-03

申请号：US11174544

申请日：2005-07-06

申请人： Niichi Itoh

发明人： Niichi Itoh

IPC分类号： G06F7/53 ,  G06F7/52 ,  G06F7/533

CPC分类号： G06F7/5318

摘要： A multiplication array is divided into divided Wallace tree arrays each performing multiplication by addition in a tree-like form. An addition result is transmitted from the divided Wallace tree arrays to a final addition circuit. Thus, an interconnection line length of a critical path of a multiplication apparatus can be reduced.

摘要翻译： 乘法阵列被划分成分割的华莱士树数组，每一个都以树形的形式通过加法进行乘法运算。 相加结果从分割的华莱士树阵列传输到最终加法电路。 因此，可以减少乘法装置的关键路径的互连线路长度。

公开(公告)号：US06838770B2

公开(公告)日：2005-01-04

申请号：US09891356

申请日：2001-06-27

申请人： Niichi Itoh

发明人： Niichi Itoh

IPC分类号： G06F17/50 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/822 ,  H01L23/52 ,  H01L23/528 ,  H01L23/544 ,  H01L27/02 ,  H01L27/04 ,  H01L23/48

CPC分类号： H01L22/34 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided with dummy patterns at an originally thinner portion of each of layers, and each of these dummy patterns is electrically connected to a reference wire that is either a power-supply wire or a ground wire.