公开(公告)号：US20080168330A1

公开(公告)日：2008-07-10

申请号：US11620988

申请日：2007-01-08

申请人： Nils Graef ,  Erich F. Haratsch

发明人： Nils Graef ,  Erich F. Haratsch

IPC分类号： G06F11/16 ,  H03M13/41 ,  H03M13/45 ,  G11C29/00

CPC分类号： G11B20/18 ,  H03M13/4146

摘要： Various systems and methods for generating and/or ordering error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for ordering erasure pointers is disclosed that includes a group of N sort cells, where N is a whole number. Each of the sort cells is operable to maintain a respective error indication that includes an error value and an associated error pointer. Further, the group of N sort cells is operable to receive an incoming error indication including error value and associated error pointer, and to update the error indication of one or more of the group of N sort cells based in part on the incoming error value. The system also includes a selector circuit that is operable to allow selectable access to each of the respective error pointers maintained in the group of N sort cells.

摘要翻译： 本文公开了用于产生和/或排序错误指示的各种系统和方法。 在某些情况下，错误指示用作存储器访问系统中的擦除指针。 作为一个具体示例，公开了一种用于排序擦除指针的系统，其包括一组N个分类单元，其中N是整数。 每个分类单元可操作以维持包括错误值和相关联的错误指针的相应错误指示。 此外，N个分组单元的组可操作以接收包括错误值和相关联的错误指针的输入错误指示，并且部分地基于输入错误值来更新该N个分类单元组中的一个或多个的错误指示。 该系统还包括选择器电路，其可操作以允许对维持在N个分类单元组中的每个相应错误指针的可选择访问。

公开(公告)号：US20080077829A1

公开(公告)日：2008-03-27

申请号：US11535540

申请日：2006-09-27

申请人： Nils Graef ,  Erich F. Haratsch

发明人： Nils Graef ,  Erich F. Haratsch

IPC分类号： G11C29/00

CPC分类号： G11C7/1006 ,  G11C7/1051 ,  G11C7/1063 ,  G11C2029/0411

摘要： Various systems and methods for generating error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for generating an erasure pointer is disclosed that includes accumulating a number of error values into an overall error value, and comparing the overall error value to an error threshold. When the overall error value exceeds the error threshold, an erasure pointer is generated. In one particular case, the error values are derived from a look up table using thermometer codes generated by an analog to digital converter. In other cases, the error values are derived from comparing a soft output with a reliability threshold.

摘要翻译： 本文公开了用于产生误差指示的各种系统和方法。 在某些情况下，错误指示用作存储器访问系统中的擦除指针。 作为一个具体示例，公开了一种用于生成擦除指针的系统，其包括将多个错误值累积到总体错误值中，并将整体误差值与错误阈值进行比较。 当总体错误值超过错误阈值时，产生擦除指针。 在一个特定情况下，使用由模数转换器产生的温度计代码从查找表中导出误差值。 在其他情况下，误差值是通过将软输出与可靠性阈值进行比较得出的。

公开(公告)号：US20110216586A1

公开(公告)日：2011-09-08

申请号：US13001310

申请日：2009-06-30

申请人： Nils Graef ,  Erich F. Haratsch ,  Milos Ivkovic ,  Victor Krachkovsky ,  Andrei Vityaev ,  Johnson Yen

发明人： Nils Graef ,  Erich F. Haratsch ,  Milos Ivkovic ,  Victor Krachkovsky ,  Andrei Vityaev ,  Johnson Yen

IPC分类号： G11C16/12 ,  G11C16/04 ,  G11C16/26

CPC分类号： G11C16/3427 ,  G06F11/1072 ,  G11C5/00 ,  G11C7/02 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3418

摘要： Methods and apparatus are provided for intercell interference mitigation using modulation coding. During programming of a flash memory, a modulation encoding is performed that selects one or more levels for programming the flash memory such that a reduced number of cells in the flash memory are programmed with a value that violates one or more predefined criteria. During a reading of a flash memory, a modulation decoding is performed that assigns one or more levels to cells in the flash memory such that a reduced number of cells in the flash memory are read with a value that violates one or more predefined criteria. The predefined criteria can be based, for example, on one or more of an amount of disturbance caused by the programmed cell; a voltage shift of a programmed cell: a voltage stored by a programmed cell; an amount of change in current through a programmed cell; and an amount of current through a programmed cell.

摘要翻译： 提供了使用调制编码的小区间干扰减轻的方法和装置。 在闪速存储器的编程期间，执行调制编码，其选择用于编程闪速存储器的一个或多个级别，使得闪存中的减少数量的单元被编程为具有违反一个或多个预定标准的值。 在读取闪速存储器期间，执行调制解码，其向闪存中的单元分配一个或多个电平，使得闪存中的单元数目减少，其值违反一个或多个预定准则。 预定义的标准可以例如基于由编程的小区引起的干扰量的一个或多个; 编程单元的电压偏移：由编程单元存储的电压; 通过编程单元的电流变化量; 以及通过编程单元的电流量。

公开(公告)号：US07702989B2

公开(公告)日：2010-04-20

申请号：US11535540

申请日：2006-09-27

申请人： Nils Graef ,  Erich F. Haratsch

发明人： Nils Graef ,  Erich F. Haratsch

IPC分类号： H03M13/00 ,  G06F11/00 ,  G11C29/00

CPC分类号： G11C7/1006 ,  G11C7/1051 ,  G11C7/1063 ,  G11C2029/0411

摘要： Various systems and methods for generating error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for generating an erasure pointer is disclosed that includes accumulating a number of error values into an overall error value, and comparing the overall error value to an error threshold. When the overall error value exceeds the error threshold, an erasure pointer is generated. In one particular case, the error values are derived from a look up table using thermometer codes generated by an analog to digital converter. In other cases, the error values are derived from comparing a soft output with a reliability threshold.

摘要翻译： 本文公开了用于产生误差指示的各种系统和方法。 在某些情况下，错误指示用作存储器访问系统中的擦除指针。 作为一个具体示例，公开了一种用于生成擦除指针的系统，其包括将多个错误值累积到总体错误值中，并将整体误差值与错误阈值进行比较。 当总体错误值超过错误阈值时，产生擦除指针。 在一个特定情况下，使用由模数转换器产生的温度计代码从查找表中导出误差值。 在其他情况下，误差值是通过将软输出与可靠性阈值进行比较得出的。

公开(公告)号：US20120290894A1

公开(公告)日：2012-11-15

申请号：US13510980

申请日：2009-11-30

申请人： Nils Graef ,  Erich F. Haratsch

发明人： Nils Graef ,  Erich F. Haratsch

IPC分类号： G06F11/10

CPC分类号： G06F13/385 ,  G06F3/0619 ,  G06F3/0656 ,  G06F5/10 ,  G06F11/1068

摘要： Methods and apparatus are provided for processing a data value in a read channel of a memory device. The data value provided to a general purpose processor for processing. The data value is not decoded data and may comprise one or more of a raw data value and an intermediate data value. The data value can be provided to the general purpose processor, for example, upon a detection of one or more predefined trigger conditions. A data value can be obtained from a memory device and then be redirected to a general purpose processor. The data value is not decoded data. The redirection can be conditionally performed if one or more predefined bypass conditions exist. The general purpose processor is optionally time-shared with one or more additional applications.

摘要翻译： 提供了用于处理存储器件的读通道中的数据值的方法和装置。 数据值提供给通用处理器进行处理。 数据值不是解码数据，并且可以包括原始数据值和中间数据值中的一个或多个。 数据值可以提供给通用处理器，例如，在检测到一个或多个预定义的触发条件时。 可以从存储器件获得数据值，然后被重定向到通用处理器。 数据值不是解码数据。 如果存在一个或多个预定义的旁路条件，则可以有条件地执行重定向。 通用处理器可选地与一个或多个附加应用程序共享。

公开(公告)号：US08797795B2

公开(公告)日：2014-08-05

申请号：US13001310

申请日：2009-06-30

申请人： Nils Graef ,  Erich F. Haratsch ,  Milos Ivkovic ,  Victor Krachkovsky ,  Andrei Vityaev ,  Johnson Yen

发明人： Nils Graef ,  Erich F. Haratsch ,  Milos Ivkovic ,  Victor Krachkovsky ,  Andrei Vityaev ,  Johnson Yen

IPC分类号： G11C16/04

CPC分类号： G11C16/3427 ,  G06F11/1072 ,  G11C5/00 ,  G11C7/02 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3418

摘要： Methods and apparatus are provided for intercell interference mitigation using modulation coding. During programming of a flash memory, a modulation encoding is performed that selects one or more levels for programming the flash memory such that a reduced number of cells in the flash memory are programmed with a value that violates one or more predefined criteria. During a reading of a flash memory, a modulation decoding is performed that assigns one or more levels to cells in the flash memory such that a reduced number of cells in the flash memory are read with a value that violates one or more predefined criteria. The predefined criteria can be based, for example, on one or more of an amount of disturbance caused by the programmed cell; a voltage shift of a programmed cell: a voltage stored by a programmed cell; an amount of change in current through a programmed cell; and an amount of current through a programmed cell.

摘要翻译： 提供了使用调制编码的小区间干扰减轻的方法和装置。 在闪速存储器的编程期间，执行调制编码，其选择用于编程闪速存储器的一个或多个级别，使得闪存中的减少数量的单元被编程为具有违反一个或多个预定标准的值。 在读取闪速存储器期间，执行调制解码，其将一个或多个级别分配给闪速存储器中的单元，使得闪存中的小数量的单元以违反一个或多个预定准则的值被读取。 预定义的标准可以例如基于由编程的小区引起的干扰量的一个或多个; 编程单元的电压偏移：由编程单元存储的电压; 通过编程单元的电流变化量; 以及通过编程单元的电流量。

公开(公告)号：US07971125B2

公开(公告)日：2011-06-28

申请号：US11620988

申请日：2007-01-08

申请人： Nils Graef ,  Erich F. Haratsch

发明人： Nils Graef ,  Erich F. Haratsch

IPC分类号： G11B20/18 ,  H03M13/45

CPC分类号： G11B20/18 ,  H03M13/4146

摘要： Various systems and methods for generating and/or ordering error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for ordering erasure pointers is disclosed that includes a group of N sort cells, where N is a whole number. Each of the sort cells is operable to maintain a respective error indication that includes an error value and an associated error pointer. Further, the group of N sort cells is operable to receive an incoming error indication including error value and associated error pointer, and to update the error indication of one or more of the group of N sort cells based in part on the incoming error value. The system also includes a selector circuit that is operable to allow selectable access to each of the respective error pointers maintained in the group of N sort cells.

摘要翻译： 本文公开了用于产生和/或排序错误指示的各种系统和方法。 在某些情况下，错误指示用作存储器访问系统中的擦除指针。 作为一个具体示例，公开了一种用于排序擦除指针的系统，其包括一组N个分类单元，其中N是整数。 每个分类单元可操作以维持包括错误值和相关联的错误指针的相应错误指示。 此外，N个分组单元的组可操作以接收包括错误值和相关联的错误指针的输入错误指示，并且部分地基于输入错误值来更新该N个分类单元组中的一个或多个的错误指示。 该系统还包括选择器电路，其可操作以允许对维持在N个分类单元组中的每个相应错误指针的可选择访问。

公开(公告)号：US09753877B2

公开(公告)日：2017-09-05

申请号：US13510980

申请日：2009-11-30

申请人： Nils Graef ,  Erich F. Haratsch

发明人： Nils Graef ,  Erich F. Haratsch

IPC分类号： G06F3/00 ,  G06F13/38 ,  G06F11/10 ,  G06F3/06 ,  G06F5/10

CPC分类号： G06F13/385 ,  G06F3/0619 ,  G06F3/0656 ,  G06F5/10 ,  G06F11/1068

摘要： Methods and apparatus are provided for processing a data value in a read channel of a memory device. The data value provided to a general purpose processor for processing. The data value is not decoded data and may comprise one or more of a raw data value and an intermediate data value. The data value can be provided to the general purpose processor, for example, upon a detection of one or more predefined trigger conditions. A data value can be obtained from a memory device and then be redirected to a general purpose processor. The data value is not decoded data. The redirection can be conditionally performed if one or more predefined bypass conditions exist. The general purpose processor is optionally time-shared with one or more additional applications.

公开(公告)号：US08578256B2

公开(公告)日：2013-11-05

申请号：US12427786

申请日：2009-04-22

申请人： Nils Graef

发明人： Nils Graef

IPC分类号： G06F11/10

CPC分类号： H03M13/116 ,  H03M13/1122 ,  H03M13/114 ,  H04L1/0051 ,  H04L1/0057

摘要： In one embodiment, a signal-processing receiver has an upstream processor and a low-density parity-check (LDPC) decoder for decoding LDPC-encoded codewords. The upstream processor generates a soft-output value for each bit of the received codewords. The LDPC decoder is implemented to process the soft-output values without having to wait until all of the soft-output values are generated for the current codeword. Further, the LDPC code used to encode the codewords is arranged to support such processing. By processing the soft-output values without having to wait until all of the soft-output values are generated for the current codeword, receivers of the present invention may have a lower latency and higher throughput than prior-art receivers that wait until all of the soft-output values are generated prior to performing LDPC decoding. In another embodiment, the LDPC decoder processes the soft-output values as soon as, and in the order that, they are generated.

摘要翻译： 在一个实施例中，信号处理接收机具有用于解码LDPC编码码字的上行处理器和低密度奇偶校验（LDPC）解码器。 上游处理器为接收到的码字的每个比特生成软输出值。 实现LDPC解码器来处理软输出值，而不必等待直到为当前码字生成所有软输出值。 此外，用于编码码字的LDPC码被布置成支持这样的处理。 通过处理软输出值而不必等待所有软输出值为当前码字生成，本发明的接收机可以具有比现有技术的接收机更低的等待时间和更高的吞吐量， 在执行LDPC解码之前产生软输出值。 在另一个实施例中，LDPC解码器按照它们被生成的顺序处理软输出值。

公开(公告)号：US08014196B2

公开(公告)日：2011-09-06

申请号：US12200129

申请日：2008-08-28

申请人： Nils Graef

发明人： Nils Graef

IPC分类号： G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26

CPC分类号： G11C7/1006 ,  G11C11/5628 ,  G11C2211/5622

摘要： In one embodiment, a mobile electronic device has a host controller, an energy-saving encoder, an energy-saving decoder, and a multi-level cell (MLC) NAND flash memory. The host controller provides raw user data to the energy-saving encoder in k-bit segments. The energy-saving encoder encodes each k-bit segment into an n-bit segment of encoded user data for programming the MLC NAND flash memory as a p-symbol codeword, where (i) k is smaller than n (ii) p(=n/log2 m) MLCs are used to store the p-symbol codeword (iii) each MLC stores one symbol of the codeword. The energy-saving decoder is adapted to read p-symbol codewords from the MLC NAND flash memory and decode each p-symbol codeword into a k-bit segment of raw user data for provision to the host controller. The host controller is adapted to vary k and n to conserve usage of power or memory-space, as needed.

摘要翻译： 在一个实施例中，移动电子设备具有主机控制器，节能编码器，节能解码器和多电平单元（MLC）NAND闪速存储器。 主机控制器以k位分段向节能编码器提供原始用户数据。 节能编码器将每个k比特段编码为编码用户数据的n比特段，用于将MLC NAND闪存编程为p符号码字，其中（i）k小于n（ii）p（= n / log2 m）MLC用于存储p符号码字（iii），每个MLC存储码字的一个符号。 节能解码器适于从MLC NAND闪速存储器读取p符号码字，并将每个p符号码字解码为原始用户数据的k比特段以提供给主机控制器。 主机控制器适于根据需要改变k和n以节省功率或存储空间的使用。