公开(公告)号：US07759984B2

公开(公告)日：2010-07-20

申请号：US11785214

申请日：2007-04-16

申请人： Noboru Takeuchi ,  Takahiro Inoue

发明人： Noboru Takeuchi ,  Takahiro Inoue

IPC分类号： H03K5/22

CPC分类号： H03K5/1252 ,  H03K3/0377 ,  H03K5/088

摘要： A comparing circuit of the present invention includes: a charging and discharging circuit to charge a capacitor with charging current and discharge the capacitor with discharging current alternately in response to a switch of an input pulse signal; a comparator circuit to compare a capacitor-voltage (Csig) of the capacitor with a first threshold voltage (Vth1) and the capacitor-voltage (Csig) with a second threshold voltage (Vth2), which is higher than the first threshold voltage, to generate a pulse signal responsive to a result of this comparison, and to supply an output-signal generating circuit with the pulse signal to switch a level of an output pulse-signal; and a logical operation circuit to adjust a value of the charging current and a value of the discharging current by generating a signal that is based on the pulse signal and is to adjust the value of the charging current and the value of the discharging current of the charging and discharging circuit and supplying the charging and discharging circuit with the signal thus generated. This configuration makes it possible for the comparing circuit to maintain capability of preventing errors, and at the same time, improve in capability of outputting a pulse having a same period as that of an input pulse having a short pause period.

摘要翻译： 本发明的比较电路包括：充电和放电电路，用于对具有充电电流的电容器充电，并且响应于输入脉冲信号的切换而交替地对放电电流进行放电; 将电容器的电容器电压（Csig）与第一阈值电压（Vth1）和具有高于第一阈值电压的第二阈值电压（Vth2）的电容器电压（Csig）进行比较的比较器电路， 响应于该比较的结果生成脉冲信号，并且向输出信号发生电路提供脉冲信号以切换输出脉冲信号的电平; 以及逻辑运算电路，通过产生基于脉冲信号的信号来调整充电电流的值和放电电流的值，并且调整充电电流的值和放电电流的值 充电和放电电路，并向充电和放电电路提供由此产生的信号。 该配置使得比较电路可以保持防止错误的能力，同时提高输出具有与具有短暂停期的输入脉冲相同周期的脉冲的能力。

公开(公告)号：US20050152705A1

公开(公告)日：2005-07-14

申请号：US11034181

申请日：2005-01-12

申请人： Takahiro Inoue ,  Noboru Takeuchi

发明人： Takahiro Inoue ,  Noboru Takeuchi

IPC分类号： G08C23/04 ,  H03G3/10 ,  H03G3/20 ,  H03G3/30 ,  H04L27/06 ,  H04B10/06

CPC分类号： H03G3/3084 ,  G08C23/04

摘要： In a gain variable amplifier, a carrier detection circuit system, and an infrared remote-control receiver using the gain variable amplifier or the carrier detection circuit system, to each of a positive output voltage Vo1 and a negative output voltage Vo2 of an amp to be subjected to gain control, connected is an AGC circuit output current (½) Iagc which is one-half of a gain control current and is a constant current. With this arrangement, it is possible to provide the gain variable amplifier, the carrier detection circuit system, both of which can reduce noise superimposed on the gain control current, and it is also possible to provide the infrared remote-control receiver using the gain variable amplifier or the carrier detection circuit system.

摘要翻译： 在增益可变放大器，载波检测电路系统和使用增益可变放大器或载波检测电路系统的红外遥控接收器中，对于放大器的正输出电压Vo 1和负输出电压Vo 2 要进行增益控制，连接是AGC电路输出电流（½）Iagc，它是增益控制电流的一半，为恒定电流。 利用这种布置，可以提供增益可变放大器，载波检测电路系统，这两者都可以减少叠加在增益控制电流上的噪声，并且还可以使用增益变量提供红外遥控接收机 放大器或载波检测电路系统。

公开(公告)号：US07495478B2

公开(公告)日：2009-02-24

申请号：US11400364

申请日：2006-04-10

申请人： Noboru Takeuchi ,  Takahiro Inoue

发明人： Noboru Takeuchi ,  Takahiro Inoue

IPC分类号： H03F3/45

CPC分类号： H03K3/02337

摘要： A comparator circuit of the present invention includes a comparator section and a current buffer circuit. In a normal mode, a standby current outputted from the comparator section is amplified by a predetermined times at the current buffer circuit. On the other hand, the standby current is not amplified in a standby mode.

摘要翻译： 本发明的比较器电路包括比较器部分和电流缓冲电路。 在正常模式中，从比较器部分输出的待机电流在当前缓冲电路放大预定时间。 另一方面，待机电流在待机模式下不被放大。

公开(公告)号：US20070297812A1

公开(公告)日：2007-12-27

申请号：US11785214

申请日：2007-04-16

申请人： Noboru Takeuchi ,  Takahiro Inoue

发明人： Noboru Takeuchi ,  Takahiro Inoue

IPC分类号： H04B10/06

CPC分类号： H03K5/1252 ,  H03K3/0377 ,  H03K5/088

摘要： A comparing circuit of the present invention includes: a charging and discharging circuit to charge a capacitor with charging current and discharge the capacitor with discharging current alternately in response to a switch of an input pulse signal; a comparator circuit to compare a capacitor-voltage (Csig) of the capacitor with a first threshold voltage (Vth1) and the capacitor-voltage (Csig) with a second threshold voltage (Vth2), which is higher than the first threshold voltage, to generate a pulse signal responsive to a result of this comparison, and to supply an output-signal generating circuit with the pulse signal to switch a level of an output pulse-signal; and a logical operation circuit to adjust a value of the charging current and a value of the discharging current by generating a signal that is based on the pulse signal and is to adjust the value of the charging current and the value of the discharging current of the charging and discharging circuit and supplying the charging and discharging circuit with the signal thus generated. This configuration makes it possible for the comparing circuit to maintain capability of preventing errors, and at the same time, improve in capability of outputting a pulse having a same period as that of an input pulse having a short pause period.

摘要翻译： 本发明的比较电路包括：充电和放电电路，用于对具有充电电流的电容器充电，并且响应于输入脉冲信号的切换而交替地对放电电流进行放电; 比较器电路，用于将电容器的电容器电压（Csig）与第一阈值电压（Vth 1）和具有高于第一阈值电压（Vth 2）的第二阈值电压（Vth 2）的电容器电压（Csig）进行比较 以响应于该比较的结果产生脉冲信号，并且向输出信号发生电路提供脉冲信号以切换输出脉冲信号的电平; 以及逻辑运算电路，通过产生基于脉冲信号的信号来调整充电电流的值和放电电流的值，并且调整充电电流的值和放电电流的值 充电和放电电路，并向充电和放电电路提供由此产生的信号。 该配置使得比较电路可以保持防止错误的能力，同时提高输出具有与具有短暂停期的输入脉冲相同周期的脉冲的能力。

公开(公告)号：US20070200585A1

公开(公告)日：2007-08-30

申请号：US11702180

申请日：2007-02-05

申请人： Noboru Takeuchi ,  Takahiro Inoue

发明人： Noboru Takeuchi ,  Takahiro Inoue

IPC分类号： G01R31/02

CPC分类号： G01R31/2884

摘要： A semiconductor wafer of the present invention includes switch circuits each connecting a corresponding internal circuit formed in the semiconductor chip and the test pad. The semiconductor wafer also includes switch control pads which are provided in the scribing region or the semiconductor chips. Voltages of the switch control pads are pulled up or down to a voltage that is equal to a substrate voltage of the semiconductor wafer. The switch control pads are provided with signals whose voltages are different from the substrate voltage so that the switch circuits are turned on. Moreover, each of the test pads, which intervenes between the semiconductor chips adjacent to each other, is connected to at least one of said switch circuits of each of the adjacent semiconductor chips.

摘要翻译： 本发明的半导体晶片包括各自连接形成在半导体芯片中的对应的内部电路和测试焊盘的开关电路。 半导体晶片还包括设置在划线区域或半导体芯片中的开关控制焊盘。 开关控制焊盘的电压被上拉或下拉至等于半导体晶片的衬底电压的电压。 开关控制板设置有电压不同于衬底电压的信号，使得开关电路接通。 此外，介于彼此相邻的半导体芯片之间的每个测试焊盘连接到每个相邻半导体芯片的至少一个开关电路。

公开(公告)号：US07299022B2

公开(公告)日：2007-11-20

申请号：US10868810

申请日：2004-06-17

申请人： Takahiro Inoue ,  Noboru Takeuchi

发明人： Takahiro Inoue ,  Noboru Takeuchi

IPC分类号： H04B1/06 ,  H03D3/24

CPC分类号： H03G3/3084

摘要： A carrier detecting circuit which generates a carrier detection level by integral action based on a reception signal and detects using the carrier detection level whether a carrier exists is disclosed and includes an integration capacitor that is charged and discharged using a difference current between a current charged from a charging circuit and a current discharged to a discharging circuit, where the charging circuit and the discharging circuit are provided in an integrator which performs the integral action.

摘要翻译： 一种载波检测电路，其基于接收信号通过积分动作生成载波检测电平，并且使用载波检测电平检测载波是否存在，并且包括使用从 充电电路和放电到放电电路的电流，其中充电电路和放电电路设置在执行积分作用的积分器中。

公开(公告)号：US20060232900A1

公开(公告)日：2006-10-19

申请号：US11400364

申请日：2006-04-10

申请人： Noboru Takeuchi ,  Takahiro Inoue

发明人： Noboru Takeuchi ,  Takahiro Inoue

IPC分类号： H02H3/20

CPC分类号： H03K3/02337

摘要： A comparator circuit of the present invention includes a comparator section and a current buffer circuit. In a normal mode, a standby current outputted from the comparator section is amplified by a predetermined times at the current buffer circuit. On the other hand, the standby current is not amplified in a standby mode.

公开(公告)号：US20050003786A1

公开(公告)日：2005-01-06

申请号：US10868810

申请日：2004-06-17

申请人： Takahiro Inoue ,  Noboru Takeuchi

发明人： Takahiro Inoue ,  Noboru Takeuchi

IPC分类号： H03D1/10 ,  H03G3/30 ,  H04L27/06 ,  H04B1/06 ,  H04B1/16 ,  H04B7/00

CPC分类号： H03G3/3084

摘要： A conventional carrier detecting circuit which generates a carrier detection level by integral action based on a reception signal and detects using the carrier detection level whether a carrier exists is arranged to charge and discharge in the following manner, an integration capacitor in an integrator that performs the integral action. Namely, the integration capacitor is (i) either charged or discharged in accordance with a result of the discrimination of the reception signal at the carrier detection level, or (ii) charged in accordance with the result of the discrimination while the integration capacitor is constantly discharged at a constant level. In contrast, a carrier detecting circuit of the present invention is arranged so that the integration capacitor is both charged and discharged constantly at a level that varies in accordance with the result of the discrimination. In other words, the integration capacitor is charged and discharged using a difference current between a current charged from a charging circuit and a current discharged to a discharging circuit. With this, it is possible to reduce the chip area without causing problems due to the reduction of the currents flowing through the transistors.

摘要翻译： 通过基于接收信号的积分动作生成载波检测电平的传统载波检测电路，并且使用载波检测电平检测是否存在载波被布置为以下列方式对放电进行充放电：积分器中的积分电容器执行 积分行动。 也就是说，积分电容器是（i）根据载波检测电平的接收信号的鉴别结果进行充电或放电，或者（ii）在积分电容器不断地根据判别结果进行充电的情况下 以恒定水平排放。 相反，本发明的载波检测电路被布置成使得积分电容器被以恒定的方式被充放电，其电平根据鉴别结果而变化。 换句话说，使用从充电电路充电的电流与放电电路放电的电流之间的差电流对积分电容器进行充放电。 由此，可以减少芯片面积而不会由于流过晶体管的电流的减少而引起问题。

公开(公告)号：US20120104530A1

公开(公告)日：2012-05-03

申请号：US13378617

申请日：2010-02-18

申请人： Seiji Kaneko ,  Masahiro Fujiwara ,  Hiroshi Aichi ,  Noboru Takeuchi

发明人： Seiji Kaneko ,  Masahiro Fujiwara ,  Hiroshi Aichi ,  Noboru Takeuchi

IPC分类号： H01L27/146

CPC分类号： G06F3/0412 ,  G02F1/133514 ,  G02F1/1362 ,  G02F2001/13312 ,  G02F2201/52 ,  G06F3/042 ,  H01L27/3227 ,  H01L27/323

摘要： A display panel substrate includes a plurality of pixels, a pixel in the display panel substrate including a PIN diode for conducting therethrough a different electric current in accordance with an amount of light received by the light receiving element, a first inorganic insulating film formed on the PIN diode, a line formed on or above the first inorganic insulating film and electrically connected to the PIN diode, an organic insulating film formed on or above the line, a transparent pixel electrode formed on the organic insulating film, and a transparent cover electrode provided at such a position that the transparent electrode is located between the organic insulating film and the first inorganic insulating film and formed to cover at least a part of an I-layer of the PIN diode.

摘要翻译： 显示面板基板包括多个像素，所述显示面板基板中的像素包括PIN二极管，用于根据由所述光接收元件接收的光量而导致不同的电流;第一无机绝缘膜，形成在所述第二无机绝缘膜上; PIN二极管，形成在第一无机绝缘膜上或上方并与PIN二极管电连接的线，形成在线上或上方的有机绝缘膜，形成在有机绝缘膜上的透明像素电极，以及设置有透明盖电极 在透明电极位于有机绝缘膜和第一无机绝缘膜之间并形成以覆盖PIN二极管的I层的至少一部分的位置。

公开(公告)号：US20070023792A1

公开(公告)日：2007-02-01

申请号：US11478854

申请日：2006-07-03

申请人： Yoshiji Takamura ,  Noboru Takeuchi ,  Satoru Yamagata

发明人： Yoshiji Takamura ,  Noboru Takeuchi ,  Satoru Yamagata

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L21/28123 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823481

摘要： In a transistor of the invention, at a boundary between gate oxide 112 formed on a silicon substrate 101 of a device formation region 10 and a device isolation film 110 adjoining the gate oxide 112, a thickness D′ of the gate electrode 114 is set larger than a uniform thickness D of the gate electrode 114 on the gate oxide 112. A height difference A between a surface of the gate oxide 112 and a surface of the device isolation film 110, a width B of a step portion 110b of the device isolation film, and the thickness D of the gate electrode 114 in its uniform-thickness portion satisfy relationships that D>B and A/D+(1−(B/D)2 )0.5>1. By ion implantation via the gate electrode 114 and the gate oxide 112, an impurity is added into a surface portion of the silicon substrate 101 at an end portion 11 of the device formation region, the impurity having concentrations higher than in the surface portion of the silicon substrate 101 in the electrode uniform portion 12 of the device formation region. The transistor can be prevented from occurrence of the inverse narrow channel effect and kink characteristics, thus being suitable for scale-down of LSIs, and yet can be manufactured with less steps.

摘要翻译： 在本发明的晶体管中，在器件形成区域10的硅衬底101上形成的栅极氧化物112与邻接栅极氧化物112的器件隔离膜110之间的边界处，栅电极114的厚度D' 比栅极氧化物112上的栅电极114的均匀厚度D。栅极氧化物112的表面和器件隔离膜110的表面之间的高度差A，器件隔离膜110的台阶部分110b的宽度B 隔离膜，并且均匀厚度部分中的栅电极114的厚度D满足D> B和A / D +（1-（B / D）≤0.2）的关系， / SUP >> 1。 通过栅电极114和栅极氧化物112的离子注入，在器件形成区域的端部11处，在硅衬底101的表面部分添加杂质，杂质浓度高于器件形成区域的表面部分 硅基板101在器件形成区域的电极均匀部分12中。 可以防止晶体管发生反向窄通道效应和扭结特性，因此适合于LSI的缩小，而且可以以较少的步骤制造。