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公开(公告)号：US20070023792A1
公开(公告)日：2007-02-01
申请号：US11478854
申请日：2006-07-03
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L21/28123 , H01L21/2652 , H01L21/266 , H01L21/76224 , H01L21/823481
摘要： In a transistor of the invention, at a boundary between gate oxide 112 formed on a silicon substrate 101 of a device formation region 10 and a device isolation film 110 adjoining the gate oxide 112, a thickness D′ of the gate electrode 114 is set larger than a uniform thickness D of the gate electrode 114 on the gate oxide 112. A height difference A between a surface of the gate oxide 112 and a surface of the device isolation film 110, a width B of a step portion 110b of the device isolation film, and the thickness D of the gate electrode 114 in its uniform-thickness portion satisfy relationships that D>B and A/D+(1−(B/D)2 )0.5>1. By ion implantation via the gate electrode 114 and the gate oxide 112, an impurity is added into a surface portion of the silicon substrate 101 at an end portion 11 of the device formation region, the impurity having concentrations higher than in the surface portion of the silicon substrate 101 in the electrode uniform portion 12 of the device formation region. The transistor can be prevented from occurrence of the inverse narrow channel effect and kink characteristics, thus being suitable for scale-down of LSIs, and yet can be manufactured with less steps.
摘要翻译： 在本发明的晶体管中，在器件形成区域10的硅衬底101上形成的栅极氧化物112与邻接栅极氧化物112的器件隔离膜110之间的边界处，栅电极114的厚度D' 比栅极氧化物112上的栅电极114的均匀厚度D。栅极氧化物112的表面和器件隔离膜110的表面之间的高度差A，器件隔离膜110的台阶部分110b的宽度B 隔离膜，并且均匀厚度部分中的栅电极114的厚度D满足D> B和A / D +（1-（B / D）≤0.2）的关系， / SUP >> 1。 通过栅电极114和栅极氧化物112的离子注入，在器件形成区域的端部11处，在硅衬底101的表面部分添加杂质，杂质浓度高于器件形成区域的表面部分 硅基板101在器件形成区域的电极均匀部分12中。 可以防止晶体管发生反向窄通道效应和扭结特性，因此适合于LSI的缩小，而且可以以较少的步骤制造。
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公开(公告)号：US07560775B2
公开(公告)日：2009-07-14
申请号：US11478854
申请日：2006-07-03
IPC分类号： H01L27/088
CPC分类号： H01L21/28123 , H01L21/2652 , H01L21/266 , H01L21/76224 , H01L21/823481
摘要： In a transistor of the invention, at a boundary between gate oxide 112 formed on a silicon substrate 101 of a device formation region 10 and a device isolation film 110 adjoining the gate oxide 112, a thickness D′ of the gate electrode 114 is set larger than a uniform thickness D of the gate electrode 114 on the gate oxide 112. A height difference A between a surface of the gate oxide 112 and a surface of the device isolation film 110, a width B of a step portion 110b of the device isolation film, and the thickness D of the gate electrode 114 in its uniform-thickness portion satisfy relationships that D>B and A/D+(1−(B/D)2)0.5>1. By ion implantation via the gate electrode 114 and the gate oxide 112, an impurity is added into a surface portion of the silicon substrate 101 at an end portion 11 of the device formation region, the impurity having concentrations higher than in the surface portion of the silicon substrate 101 in the electrode uniform portion 12 of the device formation region. The transistor can be prevented from occurrence of the inverse narrow channel effect and kink characteristics, thus being suitable for scale-down of LSIs, and yet can be manufactured with less steps.
摘要翻译： 在本发明的晶体管中，在形成在器件形成区域10的硅衬底101上的栅极氧化物112与邻接栅极氧化物112的器件隔离膜110之间的边界处，栅电极114的厚度D' 比栅极氧化物112上的栅电极114的均匀厚度D。栅极氧化物112的表面和器件隔离膜110的表面之间的高度差A，器件隔离的台阶部分110b的宽度B 膜和均匀厚度部分中的栅电极114的厚度D满足D> B和A / D +（1-（B / D）2）0.5> 1的关系。 通过栅电极114和栅极氧化物112的离子注入，在器件形成区域的端部11处，在硅衬底101的表面部分添加杂质，杂质浓度高于器件形成区域的表面部分 硅基板101在器件形成区域的电极均匀部分12中。 可以防止晶体管发生反向窄通道效应和扭结特性，因此适合于LSI的缩小，而且可以以较少的步骤制造。
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公开(公告)号：US20050141276A1
公开(公告)日：2005-06-30
申请号：US11019474
申请日：2004-12-23
申请人： Noboru Takeuchi , Satoru Yamagata , Shinichi Sato
发明人： Noboru Takeuchi , Satoru Yamagata , Shinichi Sato
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G11C16/0416 , H01L27/11521
摘要： A semiconductor memory device including: a semiconductor substrate; a plurality of memory cells arranged in a matrix having columns and rows on the semiconductor substrate and each including a source, a drain and a control gate; a plurality of insulative device isolation layers positioned in a surface portion of the substrate as extending in a column direction for isolating the memory cells arranged in each row of the matrix; a plurality of word lines positioned on the substrate as extending in a row direction and each constituted by the control gates of the memory cells of the each row which are connected in series; the source and the drain of each of the memory cells of the each row being positioned in the surface portion of the substrate on opposite sides of a corresponding one of the word lines between an adjacent pair of insulative device isolation layers; and a common source line positioned on the substrate between an adjacent pair of word lines with the intervention of side wall films positioned on side walls of the word lines as extending across the insulative device isolation layers and connecting the sources of the memory cells of the each row in series.
摘要翻译： 一种半导体存储器件，包括：半导体衬底; 在半导体衬底上布置成具有列和行的矩阵的多个存储单元，每个存储单元包括源极，漏极和控制栅极; 多个绝缘体隔离层，位于基板的表面部分中，沿列方向延伸，用于隔离布置在矩阵的每一行中的存储单元; 位于所述基板上的多个字线，沿着行方向延伸，并且各自由串联连接的各行的存储单元的控制栅极构成; 每行的每个存储单元的源极和漏极位于相邻的一对绝缘器件隔离层之间的对应的一条字线的相对侧上的衬底的表面部分中; 以及位于相邻的一对字线之间的衬底上的公共源极线，其中侧壁膜的介入位于字线的侧壁上，延伸穿过绝缘器件隔离层并连接每个字线的存储器单元的源 排列。
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公开(公告)号：US20120104530A1
公开(公告)日：2012-05-03
申请号：US13378617
申请日：2010-02-18
IPC分类号： H01L27/146
CPC分类号： G06F3/0412 , G02F1/133514 , G02F1/1362 , G02F2001/13312 , G02F2201/52 , G06F3/042 , H01L27/3227 , H01L27/323
摘要： A display panel substrate includes a plurality of pixels, a pixel in the display panel substrate including a PIN diode for conducting therethrough a different electric current in accordance with an amount of light received by the light receiving element, a first inorganic insulating film formed on the PIN diode, a line formed on or above the first inorganic insulating film and electrically connected to the PIN diode, an organic insulating film formed on or above the line, a transparent pixel electrode formed on the organic insulating film, and a transparent cover electrode provided at such a position that the transparent electrode is located between the organic insulating film and the first inorganic insulating film and formed to cover at least a part of an I-layer of the PIN diode.
摘要翻译： 显示面板基板包括多个像素，所述显示面板基板中的像素包括PIN二极管，用于根据由所述光接收元件接收的光量而导致不同的电流;第一无机绝缘膜，形成在所述第二无机绝缘膜上; PIN二极管，形成在第一无机绝缘膜上或上方并与PIN二极管电连接的线，形成在线上或上方的有机绝缘膜，形成在有机绝缘膜上的透明像素电极，以及设置有透明盖电极 在透明电极位于有机绝缘膜和第一无机绝缘膜之间并形成以覆盖PIN二极管的I层的至少一部分的位置。
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5.发明授权Method for evaluating dependence of properties of semiconductor substrate on plane orientation and semiconductor device using the same 有权用于评估半导体衬底的性能对平面取向的依赖性的方法和使用其的半导体器件公开(公告)号：US07141506B2
公开(公告)日：2006-11-28
申请号：US10175076
申请日：2002-06-20
IPC分类号： H01L21/302
CPC分类号： H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A method for evaluating a plane orientation dependence of a semiconductor substrate comprises: forming a hard mask on a semiconductor substrate having plane orientation (100); anisotropically etching the semiconductor substrate with use of the hard mask as a mask to obtain a surface oriented in a specific crystal orientation; and evaluating a plane orientation dependence of the semiconductor substrate by use of at least a portion of the surface oriented in a specific crystal orientation.
摘要翻译： 用于评估半导体衬底的平面取向依赖性的方法包括：在具有平面取向的半导体衬底上形成硬掩模（100）; 使用硬掩模作为掩模对半导体衬底进行各向异性蚀刻，以获得以特定晶体取向的表面; 以及通过使用以特定晶体取向取向的至少一部分表面来评估半导体衬底的平面取向依赖性。
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公开(公告)号：US07135726B2
公开(公告)日：2006-11-14
申请号：US09925952
申请日：2001-08-10
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/11568 , G11C16/0483 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/10864 , H01L27/11 , H01L27/1104 , H01L27/115 , H01L27/11556 , H01L27/1203 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A semiconductor memory comprises: a fist conductivity type semiconductor substrate and one or more memory cells constituted of an island-like semiconductor layer, a charge storage layer and a control gate, the charge storage layer and the control gate being formed to entirely or partially encircle a sidewall of the island-like semiconductor layer, wherein at least one of said one or more memory cells is electrically insulated from the semiconductor substrate.
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7.发明授权公开(公告)号：US06593231B2
公开(公告)日：2003-07-15
申请号：US10093712
申请日：2002-03-11
IPC分类号： H01L214763
CPC分类号： G01N23/04
摘要： A process of manufacturing an electron microscopic sample comprising the steps of: (a) forming a mask layer for covering an object region to be analyzed of a semiconductor layer and/or a conductive layer which have/has been patterned into a desired configuration; (b) reducing a periphery region surrounded the object region to be analyzed in a depth direction by using the mask layer; (c) removing the mask layer and forming an etch stop layer over the object region to be analyzed and the periphery region; and (d) polishing the semiconductor layer and/or the conductive layer in the object region to be analyzed down to the level of the surface of etch stop layer lying on the reduced periphery region.
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公开(公告)号：US4892387A
公开(公告)日：1990-01-09
申请号：US221874
申请日：1988-07-20
摘要： The present invention is directed to a light controlling sheet in use for optical indicators which comprises louver elements including an arbitrary pattern of walls which are parallel to each other and so opaque as to absorb incident light; transparent layers for permitting the incident light to pass therethrough and light reflection layers for reflecting the incident light. The transparent layers and the light reflection layers are mutually interposed between the walls of the louver element. The oblique light from the light source strikes the side surfaces of the walls, while the substantially parallel light from the light source passes through the transparent layers toward the observer. The extraneous light is reflected at the front surface of the light reflection layers so that the light controlling sheet is bright and stands out clearly.
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公开(公告)号：US4772097A
公开(公告)日：1988-09-20
申请号：US918903
申请日：1986-10-15
摘要： The present invention is directed to a light controlling sheet in use for optical indicators which comprises louver elements including an arbitrary pattern of walls which are parallel to each other and so opaque as to absorb incident light; transparent layers for permitting the incident light to pass therethrough and light reflection layers for reflecting the incident light. The transparent layers and the light reflection layers are mutually interposed between the walls of the louver element. The oblique light from the light souce strikes the side surfaces of the walls, while the substantially parallel light from the light source passes through the transparent layers toward the observer. The extraneous light is reflected at the front surface of the light reflection layers so that the light controlling sheet is bright and stands out clearly.
摘要翻译： 本发明涉及一种用于光学指示器的光控制片，其包括彼此平行并且不透明以吸收入射光的任意图案的百叶窗元件; 允许入射光通过的透明层和用于反射入射光的光反射层。 透明层和光反射层相互插入在百叶窗元件的壁之间。 来自光源的倾斜光撞击壁的侧表面，而来自光源的基本平行的光穿过透明层朝向观察者。 外光在光反射层的前表面被反射，使得光控板明亮并显着地突出。
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公开(公告)号：US4228944A
公开(公告)日：1980-10-21
申请号：US954284
申请日：1978-10-24
CPC分类号： B23K1/19 , B22F7/06 , B23K35/001 , B23K35/34
摘要： Substrates made of a metal or an alloy are bonded by coating a brazing flux incorporating a metallic powder or a metal compound powder on the surface of the substrate having a melting point of higher than 700.degree. C.; and heating them at a temperature higher than a melting point of the flux but lower than a melting point of the metal of the metallic powder or the metal compound powder whereby a molten crystallization and a mutual diffusion are caused between the substrates and the metal activated by the molten flux.
摘要翻译： 通过在熔点高于700℃的基材的表面上涂布含有金属粉末或金属化合物粉末的钎焊剂，将由金属或合金构成的基板粘合。 并在高于熔剂的熔点但低于金属粉末或金属化合物粉末的金属的熔点的温度下加热，由此在基板和由基板之间激活的金属之间引起熔融结晶和相互扩散 熔融焊剂。
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