公开(公告)号：US20210089491A1

公开(公告)日：2021-03-25

申请号：US16956105

申请日：2018-12-20

申请人： Nordic Semiconductor ASA

发明人： Ville MERIÖ

IPC分类号： G06F15/167 ,  G06F1/3206 ,  G06F9/38 ,  G06F9/54

摘要： An electronic device comprises a first processor and a second processor. An interprocessor communication module is connected to the processors and comprises a high priority mailbox and a low priority mailbox. The first processor sends a high or low priority message to the second processor. The first processor is arranged such that if it has a high priority message to send to the second processor, the first processor places the high priority message in the high priority mailbox and sends an interrupt request to the second processor. However, when the first processor has a low priority message to send to the second processor, the first processor places the high priority message in the low priority mailbox to be checked later without sending an interrupt request to the second processor.

公开(公告)号：US20200348715A1

公开(公告)日：2020-11-05

申请号：US16961209

申请日：2019-01-14

申请人： Nordic Semiconductor ASA

发明人： Ville MERIÖ

IPC分类号： G06F1/04 ,  G06F1/3237 ,  H04W52/02

摘要： A circuit system comprises a processor, a first clock with a first frequency, a second clock with a second frequency, such second frequency being higher than said first frequency and a clock calibration module. The clock calibration module comprises a plurality of counters configured to count cycles of the second clock when triggered. Each of the plurality of counters is configured to be triggered at successive cycles of the first clock. Each of the plurality of counters is configured, after a predetermined number of cycles of the first clock, to output a count of elapsed second clock cycles and the processor is configured to determine, using the counts outputted by the plurality of counters, a ratio between the first frequency and the second frequency.

公开(公告)号：US20220236873A1

公开(公告)日：2022-07-28

申请号：US17580050

申请日：2022-01-20

申请人： NORDIC SEMICONDUCTOR ASA

发明人： Ville MERIÖ

IPC分类号： G06F3/06

摘要： This document discloses a solution for controlling refreshing of memory resources of a dynamic random access memory. According to an aspect, there is disclosed an apparatus for a radio device, comprising: a dynamic random access memory circuit; a memory allocator configured to allocate memory resources from the dynamic random access memory circuit and to determine unallocated memory resources; a radio modem configured to communicate with the memory allocator in order to gain memory resources from the dynamic random access memory circuit; a memory refresh circuit configured to refresh the memory resources of the dynamic random access memory circuit; and a controller configured to determine, on the basis of a state change signal received from a radio modem of the radio device, that the radio modem is in an idle state and, in response to said determining, to control the memory refresh circuit to disable said refresh of the unallocated memory resources.

公开(公告)号：US20200348743A1

公开(公告)日：2020-11-05

申请号：US16762468

申请日：2018-11-12

申请人： Nordic Semiconductor ASA

发明人： Ville MERIÖ

IPC分类号： G06F1/329 ,  G06F9/48

摘要： A method of operating an integrated circuit system is provided. The integrated circuit system comprises a processor operable in at least a lower power state and a higher power state and a memory comprising instructions for executing a first task using the processor. The first task has a minimum execution interval associated therewith. The method comprises executing the first task using the processor and after the minimum execution interval has elapsed, determining whether the processor is in the higher power state. If the processor is in the higher power state after the minimum execution interval elapses, the method further comprises executing the first task using the processor and if the processor is not in the higher power state after the minimum execution interval elapses, the method further comprises not executing the first task.