公开(公告)号：US4561071A

公开(公告)日：1985-12-24

申请号：US519699

申请日：1983-08-02

申请人： Noriaki Hashimoto ,  Kanji Kubo ,  Chikahiko Izumi

发明人： Noriaki Hashimoto ,  Kanji Kubo ,  Chikahiko Izumi

IPC分类号： G06F12/08 ,  G06F12/10 ,  G11C11/40

CPC分类号： G06F12/1054

摘要： This storage system is designed to refer to a translation lookaside buffer, a buffer address array and a buffer storage in parallel. The translation lookaside buffer translates a logical address requesting memory access into a real address. The buffer storage retains part of the data retained in blocks by main storage and outputs data from M blocks in accordance with the logical address to M aligners. The buffer address array retains the addresses in MS of the data stored in each of the blocks in the buffer storage, and outputs M addresses in accordance with the logical address. A comparator compares the real addresses from the translation lookaside buffer with the addresses from the buffer address array, selects one of the outputs from the aligners, and transfers that output to a processor.

摘要翻译： 该存储系统被设计为并行地指代翻译后备缓冲器，缓冲器地址阵列和缓冲存储器。 翻译后备缓冲器将请求存储器访问的逻辑地址转换成真实地址。 缓冲存储器通过主存储保留保留在块中的数据的一部分，并且根据逻辑地址向M个对准器输出来自M个块的数据。 缓冲器地址阵列保存缓冲存储器中存储在每个块中的数据的MS中的地址，并且根据逻辑地址输出M个地址。 比较器将来自翻译后备缓冲器的实际地址与来自缓冲器地址阵列的地址进行比较，从对准器中选择一个输出，并将该输出传送到处理器。

公开(公告)号：US4631668A

公开(公告)日：1986-12-23

申请号：US460018

申请日：1983-01-21

申请人： Kanji Kubo ,  Chikahiko Izumi

发明人： Kanji Kubo ,  Chikahiko Izumi

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F13/12

CPC分类号： G06F12/0855 ,  G06F9/3824 ,  G06F9/3834

摘要： A storage system includes a storage for storing data, and a store buffer for temporarily buffering data before storing it into the storage. A store request is applied to the store buffer, and store data accompanied by the store request is applied to the store buffer. When a fetch request for the storage does not exist, the store data buffered in the store buffer is transferred from the store buffer to the storage and is stored therein.

摘要翻译： 存储系统包括用于存储数据的存储器和用于在将数据存储到存储器中之前临时缓冲数据的存储缓冲器。 存储请求被应用于存储缓冲器，并且存储伴随着存储请求的数据被应用于存储缓冲器。 当存储器的提取请求不存在时，缓冲在存储缓冲器中的存储数据从存储缓冲器传送到存储器并存储在存储器中。

公开(公告)号：US4500959A

公开(公告)日：1985-02-19

申请号：US375587

申请日：1982-05-06

申请人： Kanji Kubo ,  Tsugio Momose ,  Chikahiko Izumi

发明人： Kanji Kubo ,  Tsugio Momose ,  Chikahiko Izumi

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3812

摘要： In a data processing system having an instruction buffer, inconsistency between an instruction stored in a main memory and the same instruction present in the instruction buffer occurs at the time of a store operation to the memory if the instruction supplied to the store area of the main memory previously has been prefetched to and is present in the instruction buffer. The changing in the memory of the content of the instruction prefetched to the instruction buffer and the fact that the changed instruction is about to be executed are detected on the basis of the instruction fetch address of an instruction to be fetched from the memory to the instruction buffer, the instruction address of the next instruction to be executed, information concerning the byte position at which the instruction to be executed is stored, the store address at which the changed instruction is stored in the main storage and information concerning the byte position in the main storage of the instruction which is changed by the store operation. When the execution of the instructions proceeds to the changed instruction, the content of the instruction buffer is invalidated.

摘要翻译： 在具有指令缓冲器的数据处理系统中，存储在主存储器中的指令与存储在指令缓冲器中的相同指令之间的不一致在存储操作时发生到存储器，如果提供给主存储器的存储区域的指令 先前已经存储了存储在指令缓冲器中的存储器。 基于从存储器提取的指令的指令获取地址到指令，检测预先指定到指令缓冲器的指令的内容的存储器的改变以及要改变的指令将被执行的事实的改变 缓冲器，要执行的下一条指令的指令地址，存储有要执行的指令的字节位置的信息，改变的指令存储在主存储器中的存储地址以及关于在主存储器中的字节位置的信息 由存储操作改变的指令的主存储。 当指令的执行进行到改变的指令时，指令缓冲器的内容无效。

公开(公告)号：US4335425A

公开(公告)日：1982-06-15

申请号：US103405

申请日：1979-12-13

申请人： Humio Goto ,  Chikahiko Izumi ,  Riujiro Imai

发明人： Humio Goto ,  Chikahiko Izumi ,  Riujiro Imai

IPC分类号： G06F11/22 ,  G06F11/267 ,  G06F11/32

CPC分类号： G06F11/2236

摘要： A data processing apparatus incorporating a function referred to as the scan-out diagnosis function for reading out and checking sequentially internal states of the apparatus. In addition to the address designating means for the scan-out diagnosis function, an address register is provided which is validated in place of the address designating means only when the latter is inoperative, to thereby designate a particular flip-flop. An observing means is provided for observing continuously the state of the particular flip-flop as read out. Thus, the state of the flip-flop designated by the address register can be continually visually observed independently of the address designating means for the scan-out diagnosis function.

摘要翻译： 一种包含被称为扫描输出诊断功能的功能的数据处理装置，用于依次读出并检查装置的内部状态。 除了用于扫描诊断功能的地址指定装置之外，还提供一个地址寄存器，仅在后者不起作用时才被代替地址指定装置进行验证，从而指定特定的触发器。 提供观察装置，用于在读出时连续观察特定触发器的状态。 因此，独立于用于扫描诊断功能的地址指定装置，可以连续地目视地观察由地址寄存器指定的触发器的状态。

公开(公告)号：US4385365A

公开(公告)日：1983-05-24

申请号：US10470

申请日：1979-02-08

申请人： Masahiro Hashimoto ,  Kenichi Wada ,  Chikahiko Izumi

发明人： Masahiro Hashimoto ,  Kenichi Wada ,  Chikahiko Izumi

IPC分类号： G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F9/00 ,  G06F13/00

CPC分类号： G06F9/461 ,  G06F9/3863

摘要： A data shunting and recovering device is provided to shunt and hold the data stored in a register and its address before writing the register during a delay period following generation of an interrupt. This data is then restored into the register when an instruction of recovering is given. Therefore, it is allowed to achieve the moderating effects of delaying the stopping of the stage advance in data processing upon generation of an instruction for interruption without loss of data stored in the memory prior to writing during this delay period.

摘要翻译： 提供数据分流和恢复装置，用于在产生中断之后的延迟时段期间，在写入寄存器之前分流和保持存储在寄存器中的数据及其地址。 当给出恢复指令时，该数据被恢复到寄存器中。 因此，在该延迟期间，在写入之前，在生成中断指令的同时，不会丢失存储在存储器中的数据的数据，可以实现延迟数据处理中的数据处理的停止的调节效果。

公开(公告)号：US4326248A

公开(公告)日：1982-04-20

申请号：US14274

申请日：1979-02-22

申请人： Mamoru Hinai ,  Chikahiko Izumi ,  Kazuo Hibi

发明人： Mamoru Hinai ,  Chikahiko Izumi ,  Kazuo Hibi

IPC分类号： G06F12/10 ,  G06F9/36 ,  G06F13/00

CPC分类号： G06F12/1036

摘要： A multiple virtual storage control system for a data processing system for handling a plurality of virtual spaces is disclosed. Virtual addresses indicative of addresses in the virtual spaces are translated to real addresses by a translation table. When a new virtual space is established by setting a first address or segment table origin address (STO address) of the translation table, a virtual space number is assigned to the established virtual space by an STO address stack, which comprises a definite number of registers. The number of virtual space numbers assigned is larger than the number of registers. The virtual addresses and the corresponding real addresses are stored in a high-speed address translator so that the virtual addresses are translated to the real addresses at a high speed. When an overflow of the virtual space number assigned in the STO address stack takes place, the plurality of virtual spaces registered in the high-speed address translator are simultaneously purged.

摘要翻译： 公开了一种用于处理多个虚拟空间的数据处理系统的多重虚拟存储控制系统。 通过转换表将指示虚拟空间中的地址的虚拟地址转换为实际地址。 当通过设置转换表的第一地址或段表起始地址（STO地址）来建立新的虚拟空间时，通过STO地址栈将虚拟空间号分配给所建立的虚拟空间，该STO地址栈包括一定数量的寄存器 。 分配的虚拟空间编号大于寄存器数。 虚拟地址和相应的实际地址被存储在高速地址转换器中，使得虚拟地址以高速转换成实际地址。 当发生在STO地址堆栈中分配的虚拟空间编号的溢出时，同时清除在高速地址转换器中登记的多个虚拟空间。

公开(公告)号：US4172287A

公开(公告)日：1979-10-23

申请号：US865485

申请日：1977-12-29

申请人： Shun Kawabe ,  Chikahiko Izumi ,  Toshihiko Odaka

发明人： Shun Kawabe ,  Chikahiko Izumi ,  Toshihiko Odaka

IPC分类号： G06F9/38 ,  G06F15/78 ,  G06F17/16 ,  G06F7/38 ,  G06F9/00

CPC分类号： G06F15/8061 ,  G06F9/30036 ,  G06F9/3885

摘要： A general purpose data processing apparatus is provided which is adapted also for processing vector instructions. An instruction control unit reads instructions out of a memory and decodes them. If the instructions are different from vector instructions, an arithmetic unit performs the instructed operations. If the instructions are vector instructions, the subsequent control is performed by a vector instruction control unit. The vector instruction control unit decodes the vector instructions and controls the vector operands to cause the same arithmetic unit to perform the vector operation in accordance with the vector operands. Thus, the general purpose data processing apparatus can process vector instructions at high speed.

摘要翻译： 还提供了一种适用于处理向量指令的通用数据处理装置。 指令控制单元从存储器读取指令并进行解码。 如果指令与矢量指令不同，则运算器执行指令操作。 如果指令是向量指令，则由矢量指令控制单元执行后续控制。 矢量指令控制单元解码矢量指令，并控制向量操作数，使相同的运算单元根据向量操作数执行向量运算。 因此，通用数据处理装置可以高速处理向量指令。

公开(公告)号：US4056844A

公开(公告)日：1977-11-01

申请号：US620757

申请日：1975-10-08

申请人： Chikahiko Izumi

发明人： Chikahiko Izumi

IPC分类号： G06F12/08 ,  G06F15/16 ,  G06F15/177 ,  G06F13/00

CPC分类号： G06F12/0833

摘要： In a data processing system in which a single main memory is shared by two or more basic processing units, each unit is provided with a first buffer address array which stores the addresses of data stored in the associated buffer memory and is searched by this processing unit and with second buffer address arrays which store the copy of the content of the first buffer address array and are searched by the store addresses from the other processing units, so that the information stored in the buffer memory of one processing unit may be prevented from becoming different from the information stored in the main memory when another processing unit performs a storing operation, without degrading the processing efficiency of the system.

摘要翻译： 在单个主存储器由两个或多个基本处理单元共享的数据处理系统中，每个单元设置有第一缓冲器地址阵列，其存储存储在相关联的缓冲存储器中的数据的地址，并由该处理单元 并且具有存储第一缓冲器地址阵列的内容的副本的第二缓冲器地址阵列，并且被来自其他处理单元的存储地址搜索，使得可以防止存储在一个处理单元的缓冲存储器中的信息变为 与另一个处理单元执行存储操作时存储在主存储器中的信息不同，而不降低系统的处理效率。