公开(公告)号：US4172287A

公开(公告)日：1979-10-23

申请号：US865485

申请日：1977-12-29

申请人： Shun Kawabe ,  Chikahiko Izumi ,  Toshihiko Odaka

发明人： Shun Kawabe ,  Chikahiko Izumi ,  Toshihiko Odaka

IPC分类号： G06F9/38 ,  G06F15/78 ,  G06F17/16 ,  G06F7/38 ,  G06F9/00

CPC分类号： G06F15/8061 ,  G06F9/30036 ,  G06F9/3885

摘要： A general purpose data processing apparatus is provided which is adapted also for processing vector instructions. An instruction control unit reads instructions out of a memory and decodes them. If the instructions are different from vector instructions, an arithmetic unit performs the instructed operations. If the instructions are vector instructions, the subsequent control is performed by a vector instruction control unit. The vector instruction control unit decodes the vector instructions and controls the vector operands to cause the same arithmetic unit to perform the vector operation in accordance with the vector operands. Thus, the general purpose data processing apparatus can process vector instructions at high speed.

摘要翻译： 还提供了一种适用于处理向量指令的通用数据处理装置。 指令控制单元从存储器读取指令并进行解码。 如果指令与矢量指令不同，则运算器执行指令操作。 如果指令是向量指令，则由矢量指令控制单元执行后续控制。 矢量指令控制单元解码矢量指令，并控制向量操作数，使相同的运算单元根据向量操作数执行向量运算。 因此，通用数据处理装置可以高速处理向量指令。

公开(公告)号：US4769770A

公开(公告)日：1988-09-06

申请号：US807684

申请日：1985-12-11

申请人： Hiroo Miyadera ,  Shun Kawabe ,  Hiroshi Murayama ,  Yasuhiko Hatakeyama

发明人： Hiroo Miyadera ,  Shun Kawabe ,  Hiroshi Murayama ,  Yasuhiko Hatakeyama

IPC分类号： G06F12/10 ,  G06F12/02 ,  G06F12/08 ,  G06F17/16 ,  G06F9/36 ,  G06F9/00

CPC分类号： G06F12/0284

摘要： An information processing apparatus having an address translation system includes a plurality of processors in each of which an addressing is carried out by translating a logical address into a real address in the virtual storage system for data processing. The plurality of processors include a scalar processor for translating a logical address into a real address by using an address translation table; and a vector processor for determining if the logical address to be relocated lies within a predetermined address range, for address-relocating the logical address to the real address based on a relocation table when the logical address lies within the predetermined address range, and using the logical address as a real address when the logical address lies outside of the predetermined address range. The predetermined address range and the content of the relocation table are set by the scalar processor which supervises the program storage area.

摘要翻译： 具有地址转换系统的信息处理装置包括多个处理器，每个处理器通过将逻辑地址转换为虚拟存储系统中的实际地址进行数据处理来执行寻址，用于数据处理。 多个处理器包括标量处理器，用于通过使用地址转换表将逻辑地址转换成真实地址; 以及矢量处理器，用于确定要重定位的逻辑地址是否在预定地址范围内，用于当逻辑地址位于预定地址范围内时，基于重定位表将逻辑地址重定位到实地址，并且使用 逻辑地址作为逻辑地址位于预定地址范围之外的实地址。 预定地址范围和重定位表的内容由监控程序存储区域的标量处理器设置。

公开(公告)号：US06880409B2

公开(公告)日：2005-04-19

申请号：US10679407

申请日：2003-10-07

申请人： Shun Kawabe ,  Keiichi Sato

发明人： Shun Kawabe ,  Keiichi Sato

IPC分类号： G01N3/24 ,  G01N3/02

CPC分类号： G01N3/24

摘要： A shear test apparatus for testing a shear characteristic of a curved panel is provided. The shear test apparatus includes a frame made up of first and second curved side bearing members for bearing a pair of curved sides of the curved panel and first and second flat side bearing members for bearing a pair of flat sides of the curved panel. The second curved side bearing member has an arm extending in a direction perpendicular to the face of the curved panel. The arm has an external force loading point in a position coincident with the center of shear of the curved panel, to prevent twisting of the curved panel.

摘要翻译： 提供了用于测试弯曲面板的剪切特性的剪切试验装置。 剪切试验装置包括由第一和第二弯曲侧支承构件构成的框架，用于支承曲面板的一对弯曲侧面，以及用于承载弯曲面板的一对平坦侧面的第一和第二平面侧支承构件。 第二弯曲侧支承构件具有沿垂直于弯曲面板的面的方向延伸的臂。 臂具有与弯曲面板的剪切中心重合的位置的外力加载点，以防止弯曲面板的扭曲。

公开(公告)号：US5115393A

公开(公告)日：1992-05-19

申请号：US399917

申请日：1989-08-29

申请人： Masamori Kashiyama ,  Koichi Ishii ,  Shun Kawabe ,  Masami Usami

发明人： Masamori Kashiyama ,  Koichi Ishii ,  Shun Kawabe ,  Masami Usami

IPC分类号： G06F17/16 ,  G06F9/30 ,  G06F15/78

CPC分类号： G06F15/8084 ,  G06F9/3012 ,  G06F9/30141

摘要： Vector registers having logically equal address are arranged as two banks which can independently access ultra high speed RAM's. One bank holds all even-numbered elements of vector data and the other bank holds all odd-numbered elements of the vector data. A write address generator and a read address generator which are one half as fast as a clock rate of a machine cycle and which have a phase difference of one half period therebetween are provided so that the clock rate of the machine cycle may be set to one half of a total time of a write pitch and a read pitch of the vector registers.

摘要翻译： 具有逻辑相等地址的矢量寄存器被布置为可以独立访问超高速RAM的两个存储体。 一个存储体保存矢量数据的所有偶数元素，另一个存储体保存向量数据的所有奇数元素。 提供了与机器周期的时钟速度相同的一半的写入地址发生器和读取地址生成器，并且具有一个半周期的相位差，使得机器周期的时钟速率可以被设置为1 写入音高的总时间的一半和矢量寄存器的读取音高。

公开(公告)号：US4621324A

公开(公告)日：1986-11-04

申请号：US562224

申请日：1983-12-16

申请人： Yasunori Ushiro ,  Shigeo Nagashima ,  Shun Kawabe

发明人： Yasunori Ushiro ,  Shigeo Nagashima ,  Shun Kawabe

IPC分类号： G06F17/16 ,  G06F15/80 ,  G06F13/00

CPC分类号： G06F15/8092

摘要： A vector processor provided wtih a vector register to set therein vector element data having been stored in a main storage, prior to a vector operation, is disclosed in which control information indicating whether new element data is read out from the main storage to be set in one location of the vector register capable of storing one vector element data and to be latched, or vector element data having been latched is set in the above location, is set in a mask register, for each location of the vector register, and the control information is successively read out from the mask register, to set vector element data in the vector register in accordance with the read-out control information.

摘要翻译： 向量处理器提供矢量寄存器以在其中设置已经存储在主存储器中的向量操作之前的向量元素数据，其中指示是否从主存储器读出新元素数据被设置在 对于矢量寄存器的每个位置，将能够存储一个矢量元素数据并被锁存的向量寄存器的一个位置或被锁存的向量元素数据设置在上述位置中，被设置在屏蔽寄存器中，并且控制 信息从掩模寄存器连续地读出，根据读出的控制信息在向量寄存器中设置矢量元素数据。

公开(公告)号：US3940741A

公开(公告)日：1976-02-24

申请号：US376275

申请日：1973-07-05

申请人： Hisashi Horikoshi ,  Shun Kawabe

发明人： Hisashi Horikoshi ,  Shun Kawabe

IPC分类号： G06F9/38 ,  G06F9/20

CPC分类号： G06F9/3844

摘要： An information processing device for processing instructions, including branch instructions, is characterized in that a route memory is provided for storing branch target addresses of a plurality of branch instructions and branch target instructions in corresponding relationship to the branch target addresses, and the route memory is referenced by the address in a given instruction, whereby the branch target instruction at the corresponding branch target address is read out.

摘要翻译： 一种用于处理指令的信息处理装置，包括分支指令，其特征在于，提供了一种路由存储器，用于存储多个分支指令的分支目标地址和与分支目标地址对应关系的分支目标指令，并且路由存储器 由给定指令中的地址引用，从而读出相应分支目标地址处的分支目标指令。

公开(公告)号：US6064234A

公开(公告)日：2000-05-16

申请号：US134335

申请日：1998-08-14

申请人： Noboru Masuda ,  Yoshio Miki ,  Shun Kawabe

发明人： Noboru Masuda ,  Yoshio Miki ,  Shun Kawabe

IPC分类号： H03K19/0948 ,  H03K19/094

CPC分类号： H03K19/0948

摘要： A logic circuit for use as a selector having multiple inputs and high operation speed. The logic circuit includes a first FET having a first electrode connected to a first power supply, a second electrode connected to an output terminal and a third electrode connected to an intermediate control node, and a plurality of logic blocks parallelly connected between the second power supply and the output terminal. Each logic block includes second and third FETs being of a conductivity type opposite to that of the first FET and connected in series between the output terminal and a second power supply. Each logic block also includes a fourth FET being of the same conductivity type as the second and third FETs and having a third electrode connected to the third electrode of the second FET, a first electrode connected to the third electrode of the third FET and a second electrode connected to the intermediate control node. The conduction resistance between the output terminal and the first power supply is reduced and the parasitic capacitance added to the output terminal is also reduced, thereby allowing the logic circuit to be operated at high speed.

摘要翻译： 用作具有多个输入和高操作速度的选择器的逻辑电路。 逻辑电路包括：第一FET，具有连接到第一电源的第一电极，连接到输出端子的第二电极和连接到中间控制节点的第三电极;以及并联连接在第二电源 和输出端子。 每个逻辑块包括具有与第一FET相反的导电类型的第二和第三FET，并串联连接在输出端和第二电源之间。 每个逻辑块还包括与第二和第三FET具有相同导电类型的第四FET，并且具有连接到第二FET的第三电极的第三电极，连接到第三FET的第三电极的第一电极和第二FET 电极连接到中间控制节点。 输出端子与第一电源之间的导通电阻降低，并且增加到输出端子的寄生电容也减小，从而允许逻辑电路以高速运行。

公开(公告)号：US4849882A

公开(公告)日：1989-07-18

申请号：US87603

申请日：1987-08-20

申请人： Tomoo Aoyama ,  Shun Kawabe

发明人： Tomoo Aoyama ,  Shun Kawabe

IPC分类号： G06F17/16 ,  G06F15/78

CPC分类号： G06F15/8084

摘要： A vector processor has a plurality of vector processing units each of which is connected to main storage via a plurality of memory port logic units. Each of the vector processing units has a resource management circuit, thereby managing its resources and the plurality of memory port logic units as resources and reporting information of the memory port logic unit determined to be used to other vector processing units. The plurality of memory port logic units are thus shared by the plurality of vector processing units.

摘要翻译： 矢量处理器具有多个矢量处理单元，每个矢量处理单元经由多个存储器端口逻辑单元连接到主存储器。 每个矢量处理单元具有资源管理电路，从而管理其资源和多个存储器端口逻辑单元作为确定为用于其他矢量处理单元的存储器端口逻辑单元的资源和报告信息。 因此，多个存储器端口逻辑单元由多个向量处理单元共享。

公开(公告)号：US5807454A

公开(公告)日：1998-09-15

申请号：US711678

申请日：1996-09-04

申请人： Shun Kawabe ,  Keiichi Sato ,  Daiya Yamashita ,  Haruo Nakayama ,  Koji Shiraishi ,  Keizo Matsumoto

发明人： Shun Kawabe ,  Keiichi Sato ,  Daiya Yamashita ,  Haruo Nakayama ,  Koji Shiraishi ,  Keizo Matsumoto

IPC分类号： B29C70/44 ,  B29D99/00 ,  B64C3/28 ,  B64D15/04 ,  B32B31/00

CPC分类号： B29D99/0028 ,  B29C70/443 ,  B64C3/28 ,  B64D15/04 ,  B29C2791/001 ,  Y02T50/433 ,  Y10T156/1031

摘要： A leading edge structure for an aircraft has an outer wall, an inner wall disposed within the outer wall and including a partition with, the outer wall, the inner wall and the partition jointly defining a hot-air chamber, and a plurality of flow-rectifying fins or disposed in the hot-air chamber and compartmentalizing the hot-air chamber into a plurality of hot-air passages. The outer wall and the flow-rectifying fins are made of a fiber-reinforced synthetic resin and joined to each other by curing. The inner wall and the partition comprise a single component which is made of a fiber-reinforced synthetic resin, and being bonded to the outer wall. Alternatively, the inner wall and the partition are separate from each other and are joined to each other.

摘要翻译： 用于飞行器的前缘结构具有外壁，内壁，其设置在所述外壁内，并且包括与所述外壁，所述内壁和所述隔板共同限定热空气室的隔板， 整流翅片或设置在热空气室中并将热空气室分隔成多个热空气通道。 外壁和整流翅片由纤维增强合成树脂制成，并通过固化彼此接合。 内壁和隔板包括由纤维增强合成树脂制成并且被结合到外壁的单一部件。 或者，内壁和隔板彼此分离并且彼此接合。

公开(公告)号：US4991083A

公开(公告)日：1991-02-05

申请号：US228300

申请日：1988-08-04

申请人： Tomoo Aoyama ,  Shun Kawabe

发明人： Tomoo Aoyama ,  Shun Kawabe

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F15/78 ,  G06F17/16

CPC分类号： G06F15/8084 ,  G06F12/10

摘要： A method and apparatus for extending an address space for a vector processor including a vector processing unit and a scalar processing unit. A main storage and an extended storage are also disclosed. An address translator is provided for each requestor within the vector processing unit. Each address translator includes registers for storing main storage addresses and extended storage addresses for the address translation, a register for storing information such as an invalid bit regarding an address space present on the main storage, a register for storing information such as a protection bit representative of an address translation enabled area, and registers for storing a reference bit and a write bit representative of the main storage reference status. The scalar processing unit includes an access controller for allowing a write/pad operation relative to the respective registers in the address translator. The vector processing unit includes a first logic circuit for temporarily suspending a main storage reference request sent from the requestor to an area not present on the main storage, a second logic circuit for releasing the suspension, and a third logic circuit for informing the scalar processing unit of the suspension of the main storage reference request.

摘要翻译： 一种用于扩展用于包括向量处理单元和标量处理单元的向量处理器的地址空间的方法和装置。 还公开了主存储和扩展存储。 为向量处理单元内的每个请求者提供地址转换器。 每个地址转换器包括用于存储用于地址转换的主存储地址和扩展存储地址的寄存器，用于存储关于存在于主存储器上的地址空间的无效位的信息的寄存器，用于存储诸如保护位代表 的地址转换使能区域，以及用于存储参考位和用于表示主存储器参考状态的写入位的寄存器。 标量处理单元包括访问控制器，用于允许相对于地址翻译器中的相应寄存器的写/写操作。 矢量处理单元包括：第一逻辑电路，用于将从请求者发送的主存储参考请求临时挂起到主存储器上不存在的区域;第二逻辑电路，用于释放暂停;以及第三逻辑电路，用于通知标量处理 单位暂停主存储参考请求。