公开(公告)号：US20110104870A1

公开(公告)日：2011-05-05

申请号：US12866271

申请日：2009-02-17

申请人： Norihiro Kobayashi ,  Tohru Ishizuka ,  Hiroji Aga ,  Nobuhiko Noto

发明人： Norihiro Kobayashi ,  Tohru Ishizuka ,  Hiroji Aga ,  Nobuhiko Noto

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： A method for manufacturing a bonded wafer, including at least implanting at least one type of gas ion selected from a hydrogen ion and a rare gas ion from a surface of a bond wafer to form an ion-implanted layer in the wafer, bonding an ion-implanted surface of the bond wafer to a surface of a base wafer directly or through an insulator film, and then delaminating the bond wafer at the ion-implanted layer to fabricate a bonded wafer. A plasma treatment is applied to a bonding surface of one of the bond wafer and the base wafer to grow an oxide film, etching the grown oxide film is carried out, and bonding to the other wafer is performed. The method enables preventing defects by reducing particles on the bonding surface and performing strong bonding when effecting bonding directly or through the insulator film.

摘要翻译： 一种用于制造接合晶片的方法，包括至少从接合晶片的表面注入选自氢离子和稀有气体离子的至少一种气体离子，以在晶片中形成离子注入层，将离子 将接合晶片的植入表面直接或通过绝缘体膜的基底晶片的表面，然后在离子注入层分层接合晶片以制造接合晶片。 将等离子体处理施加到接合晶片和基底晶片之一的接合表面以生长氧化膜，进行蚀刻生长的氧化物膜，并且进行与另一晶片的接合。 该方法通过在直接或通过绝缘膜进行接合的同时还原接合表面上的颗粒并进行强结合来防止缺陷。

公开(公告)号：US20110223740A1

公开(公告)日：2011-09-15

申请号：US13129538

申请日：2009-11-11

申请人： Tohru Ishizuka ,  Norihiro Kobayashi ,  Hiroji Aga ,  Nobuhiko Noto

发明人： Tohru Ishizuka ,  Norihiro Kobayashi ,  Hiroji Aga ,  Nobuhiko Noto

IPC分类号： H01L21/762

CPC分类号： H01L21/76254 ,  H01L21/84 ,  H01L22/12 ,  H01L22/20 ,  H01L29/78603

摘要： A method for manufacturing an SOI wafer having a buried oxide film with a predetermined thickness including performing a heat treatment for reducing a thickness of the buried oxide film on an SOI wafer material having an SOI layer formed on the buried oxide film, wherein a thickness of the SOI layer of the SOI wafer material to be subjected to the heat treatment for reducing the thickness of the buried oxide film is calculated on the basis of a ratio of the thickness of the buried oxide film to be reduced by the heat treatment with respect to a permissible value of an amount of change in an in-plane range of the buried oxide film, the change being caused by the heat treatment, and the SOI wafer material obtained by thinning the thickness of the bond wafer so as to have the calculated thickness of the SOI layer is subjected to the heat treatment for reducing the thickness of the buried oxide film.

摘要翻译： 一种制造具有预定厚度的具有预定厚度的掩埋氧化物膜的SOI晶片的方法，包括：在掩埋氧化膜上形成SOI层的SOI晶片材料上进行用于减小掩埋氧化膜厚度的热处理，其中， 基于通过热处理而减少的掩埋氧化膜的厚度的比率，计算要进行用于减小掩埋氧化膜的厚度的热处理的SOI晶片材料的SOI层相对于 掩埋氧化膜的面内范围的变化量的允许值，由热处理引起的变化，以及通过使接合晶片的厚度变薄而获得的SOI晶片材料，使得具有计算出的厚度 对SOI层进行热处理，以减小掩埋氧化膜的厚度。

公开(公告)号：US20100132205A1

公开(公告)日：2010-06-03

申请号：US12452070

申请日：2008-07-03

申请人： Norihiro Kobayashi ,  Tohru Ishizuka ,  Nobuhiko Noto

发明人： Norihiro Kobayashi ,  Tohru Ishizuka ,  Nobuhiko Noto

IPC分类号： G01B5/24

CPC分类号： H01L21/76251 ,  H01L22/12 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method for measuring a rotation angle of a bonded wafer, wherein a base wafer and a bond wafer each having a notch indicative of a crystal orientation formed at an outer edge thereof are bonded to each other at a desired rotation angle by utilizing the notches, a profile of the bond wafer having a reduced film thickness is observed with respect to a bonded wafer manufactured by reducing a film thickness of the bond wafer, a positional direction of the notch of the bond wafer seen from a center of the bonded wafer is calculated by utilizing the profile, an angle formed between the calculated positional direction of the notch of the bond wafer and a positional direction of the notch of the base wafer is calculated, and a rotation angle of the base wafer and the bond wafer is measured. As a result, the method for measuring a rotation angle of a bonded wafer that enables accurately and easily measuring the rotation angle of the notches of the base wafer and the bond wafer in a bonded wafer manufacturing line can be provided.

摘要翻译： 本发明提供了一种用于测量接合晶片的旋转角度的方法，其中每个具有指示在其外边缘处形成的晶体取向的切口的基底晶片和接合晶片以期望的旋转角度彼此接合， 利用缺口，观察到相对于通过降低接合晶片的膜厚而制造的接合晶片，从接合晶片的中心观察到的接合晶片的凹口的位置方向，观察到具有减小的膜厚度的接合晶片的轮廓 通过利用轮廓来计算贴合晶片，计算出计算的接合晶片的凹口的位置方向与基底晶片的凹口的位置方向之间形成的角度，以及基底晶片和接合晶片的旋转角度 被测量。 结果，可以提供用于测量接合晶片的旋转角度的方法，其能够准确且容易地测量接合晶片制造线中的基底晶片和接合晶片的切口的旋转角度。

公开(公告)号：US08097523B2

公开(公告)日：2012-01-17

申请号：US12866271

申请日：2009-02-17

申请人： Norihiro Kobayashi ,  Tohru Ishizuka ,  Hiroji Aga ,  Nobuhiko Noto

发明人： Norihiro Kobayashi ,  Tohru Ishizuka ,  Hiroji Aga ,  Nobuhiko Noto

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/76254

摘要： A method for manufacturing a bonded wafer, including at least implanting at least one type of gas ion selected from a hydrogen ion and a rare gas ion from a surface of a bond wafer to form an ion-implanted layer in the wafer, bonding an ion-implanted surface of the bond wafer to a surface of a base wafer directly or through an insulator film, and then delaminating the bond wafer at the ion-implanted layer to fabricate a bonded wafer. A plasma treatment is applied to a bonding surface of one of the bond wafer and the base wafer to grow an oxide film, etching the grown oxide film is carried out, and bonding to the other wafer is performed. The method enables preventing defects by reducing particles on the bonding surface and performing strong bonding when effecting bonding directly or through the insulator film.

摘要翻译： 一种用于制造接合晶片的方法，包括至少从接合晶片的表面注入选自氢离子和稀有气体离子的至少一种气体离子，以在晶片中形成离子注入层，将离子 将接合晶片的植入表面直接或通过绝缘体膜的基底晶片的表面，然后在离子注入层分层接合晶片以制造接合晶片。 将等离子体处理施加到接合晶片和基底晶片之一的接合表面以生长氧化膜，进行蚀刻生长的氧化物膜，并且进行与另一晶片的接合。 该方法通过在直接或通过绝缘膜进行接合的同时还原接合表面上的颗粒并进行强结合来防止缺陷。

公开(公告)号：US07861421B2

公开(公告)日：2011-01-04

申请号：US12452070

申请日：2008-07-03

申请人： Norihiro Kobayashi ,  Tohru Ishizuka ,  Nobuhiko Noto

发明人： Norihiro Kobayashi ,  Tohru Ishizuka ,  Nobuhiko Noto

IPC分类号： G01B5/24 ,  G01B7/30

CPC分类号： H01L21/76251 ,  H01L22/12 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method for measuring a rotation angle of a bonded wafer, wherein a base wafer and a bond wafer each having a notch indicative of a crystal orientation formed at an outer edge thereof are bonded to each other at a desired rotation angle by utilizing the notches, a profile of the bond wafer having a reduced film thickness is observed with respect to a bonded wafer manufactured by reducing a film thickness of the bond wafer, a positional direction of the notch of the bond wafer seen from a center of the bonded wafer is calculated by utilizing the profile, an angle formed between the calculated positional direction of the notch of the bond wafer and a positional direction of the notch of the base wafer is calculated, and a rotation angle of the base wafer and the bond wafer is measured. As a result, the method for measuring a rotation angle of a bonded wafer that enables accurately and easily measuring the rotation angle of the notches of the base wafer and the bond wafer in a bonded wafer manufacturing line can be provided.

摘要翻译： 本发明提供了一种用于测量接合晶片的旋转角度的方法，其中每个具有指示在其外边缘处形成的晶体取向的切口的基底晶片和接合晶片以期望的旋转角度彼此接合， 利用缺口，观察到相对于通过降低接合晶片的膜厚而制造的接合晶片，从接合晶片的中心观察到的接合晶片的凹口的位置方向，观察到具有减小的膜厚度的接合晶片的轮廓 通过利用轮廓来计算贴合晶片，计算出计算的接合晶片的凹口的位置方向与基底晶片的凹口的位置方向之间形成的角度，以及基底晶片和接合晶片的旋转角度 被测量。 结果，可以提供用于测量接合晶片的旋转角度的方法，其能够准确且容易地测量接合晶片制造线中的基底晶片和接合晶片的切口的旋转角度。

公开(公告)号：US20100314722A1

公开(公告)日：2010-12-16

申请号：US12867922

申请日：2009-02-19

申请人： Tohru Ishizuka ,  Nobuhiko Noto ,  Norihiro Kobayashi ,  Masatake Nakano

发明人： Tohru Ishizuka ,  Nobuhiko Noto ,  Norihiro Kobayashi ,  Masatake Nakano

IPC分类号： H01L29/04 ,  H01L21/762

CPC分类号： H01L21/76254 ,  H01L29/045 ,  H01L29/78603

摘要： The present invention is an SOI wafer comprising at least: an SOI layer; a silicon oxide film; and a base wafer, wherein the SOI layer has a plane orientation of (100), and the base wafer has a resistivity of 100 Ω·cm or more and a plane orientation different from (100). As a result, there is provided the SOI wafer and the manufacturing method thereof that have no complicated manufacturing step, defects on a bonding interface which are not practically a problem in number and a high interface state density (Dit) for trapping carriers on an interface of a BOX layer and the base wafer.

摘要翻译： 本发明是至少包括SOI层的SOI晶片; 氧化硅膜; 以及基底晶片，其中所述SOI层具有（100）的平面取向，并且所述基底晶片的电阻率为100Ω·cm·cm以上且平面取向不同于（100）。 结果，提供了没有复杂的制造步骤的SOI晶片及其制造方法，接合界面上的缺陷在数量上几乎不成问题，并且用于在接口上捕获载体的高界面态密度（Dit） 的BOX层和基底晶片。

公开(公告)号：US08697544B2

公开(公告)日：2014-04-15

申请号：US13126993

申请日：2009-10-14

申请人： Tohru Ishizuka ,  Norihiro Kobayashi ,  Nobuhiko Noto

发明人： Tohru Ishizuka ,  Norihiro Kobayashi ,  Nobuhiko Noto

IPC分类号： H01L21/30

CPC分类号： H01L21/76254

摘要： The present invention is a method for manufacturing a bonded wafer including at least the steps of: forming an ion-implanted layer inside a bond wafer; bringing the ion-implanted surface of the bond wafer into close contact with a surface of a base wafer directly or through a silicon oxide film; and performing heat treatment for delaminating the bond wafer at the ion-implanted layer, wherein the heat treatment step for delaminating includes performing a pre-annealing at a temperature of less than 500° C. and thereafter performing a delamination heat treatment at a temperature of 500° C. or more, and the pre-annealing is performed at least by a heat treatment at a first temperature and a subsequent heat treatment at a second temperature higher than the first temperature. As a result, there is provided a method for manufacturing a bonded wafer having high quality, for example, mainly the reduction of defects, by forming a high bonding strength state at a lower temperature than the temperature at which the delamination is caused, in the manufacture of the bonded wafer by the Smart Cut method (registered trademark).

摘要翻译： 本发明是一种制造接合晶片的方法，至少包括以下步骤：在接合晶片内形成离子注入层; 使接合晶片的离子注入表面直接或通过氧化硅膜与基底晶片的表面紧密接触; 以及进行用于使离子注入层剥离接合晶片的热处理，其中用于分层的热处理步骤包括在小于500℃的温度下进行预退火，然后在温度为 至少通过在第一温度下的热处理和在比第一温度高的第二温度进行随后的热处理来进行预退火。 结果，提供了一种制造高质量的接合晶片的方法，例如主要是减少缺陷，通过在比分层的温度低的温度下形成高的结合强度状态，在 通过Smart Cut方法（注册商标）制造贴合晶片。

公开(公告)号：US08466538B2

公开(公告)日：2013-06-18

申请号：US12867922

申请日：2009-02-19

申请人： Tohru Ishizuka ,  Nobuhiko Noto ,  Norihiro Kobayashi ,  Masatake Nakano

发明人： Tohru Ishizuka ,  Nobuhiko Noto ,  Norihiro Kobayashi ,  Masatake Nakano

IPC分类号： H01L29/04

CPC分类号： H01L21/76254 ,  H01L29/045 ,  H01L29/78603

摘要： The present invention is an SOI wafer comprising at least: an SOI layer; a silicon oxide film; and a base wafer, wherein the SOI layer has a plane orientation of (100), and the base wafer has a resistivity of 100 Ω·cm or more and a plane orientation different from (100). As a result, there is provided the SOI wafer and the manufacturing method thereof that have no complicated manufacturing step, defects on a bonding interface which are not practically a problem in number and a high interface state density (Dit) for trapping carriers on an interface of a BOX layer and the base wafer.

摘要翻译： 本发明是至少包括SOI层的SOI晶片; 氧化硅膜; 和基底晶片，其中所述SOI层具有（100）的平面取向，并且所述基底晶片的电阻率为100Ω·cm以上且平面取向不同于（100）。 结果，提供了没有复杂的制造步骤的SOI晶片及其制造方法，接合界面上的缺陷在数量上几乎不成问题，并且用于在接口上捕获载体的高界面态密度（Dit） 的BOX层和基底晶片。

公开(公告)号：US20120326268A1

公开(公告)日：2012-12-27

申请号：US13582614

申请日：2011-03-01

申请人： Masahiro Kato ,  Satoshi Oka ,  Norihiro Kobayashi ,  Tohru Ishizuka ,  Nobuhiko Noto

发明人： Masahiro Kato ,  Satoshi Oka ,  Norihiro Kobayashi ,  Tohru Ishizuka ,  Nobuhiko Noto

IPC分类号： H01L29/06 ,  H01L21/20 ,  H01L21/762 ,  H01L29/02

CPC分类号： H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/76254 ,  H01L29/78603

摘要： A silicon epitaxial wafer having a silicon epitaxial layer grown by vapor phase epitaxy on a main surface of a silicon single crystal substrate, wherein the main surface of the silicon single crystal substrate is tilted with respect to a [100] axis at an angle θ in a [011] direction or a [0-1-1] direction from a (100) plane and at an angle Φ in a [01-1] direction or a [0-11] direction from the (100) plane, the angle θ and the angle Φ are less than ten minutes, and a dopant concentration of the silicon epitaxial layer is equal to or more than 1×1019/cm3. Even when an epitaxial layer having a dopant concentration of 1×1019/cm3 or more is formed on the main surface of the silicon single crystal substrate, stripe-shaped surface irregularities on the epitaxial layer are inhibited.

摘要翻译： 一种硅外延片，其具有在硅单晶衬底的主表面上通过气相外延生长的硅外延层，其中所述硅单晶衬底的主表面相对于[100]轴以角度倾斜; 在（100）面的[011]方向或[0-1-1]方向上，在（100）面的[01-1]方向或[0-11]方向上的角度Φ处， 角度和角度 角度Φ小于10分钟，硅外延层的掺杂剂浓度为1×1019 / cm3以上。 即使在硅单晶衬底的主表面上形成掺杂浓度为1×1019 / cm3以上的外延层，也抑制了外延层上的条状表面凹凸。

公开(公告)号：US08823130B2

公开(公告)日：2014-09-02

申请号：US13582614

申请日：2011-03-01

申请人： Masahiro Kato ,  Satoshi Oka ,  Norihiro Kobayashi ,  Tohru Ishizuka ,  Nobuhiko Noto

发明人： Masahiro Kato ,  Satoshi Oka ,  Norihiro Kobayashi ,  Tohru Ishizuka ,  Nobuhiko Noto

IPC分类号： H01L21/70 ,  H01L21/02 ,  H01L21/762 ,  H01L29/786

CPC分类号： H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/76254 ,  H01L29/78603

摘要： A silicon epitaxial wafer having a silicon epitaxial layer grown by vapor phase epitaxy on a main surface of a silicon single crystal substrate, wherein the main surface of the silicon single crystal substrate is tilted with respect to a [100] axis at an angle θ in a [011] direction or a [0-1-1] direction from a (100) plane and at an angle φ in a [01-1] direction or a [0-11] direction from the (100) plane, the angle θ and the angle φ are less than ten minutes, and a dopant concentration of the silicon epitaxial layer is equal to or more than 1×1019/cm3. Even when an epitaxial layer having a dopant concentration of 1×1019/cm3 or more is formed on the main surface of the silicon single crystal substrate, stripe-shaped surface irregularities on the epitaxial layer are inhibited.

摘要翻译： 一种硅外延片，其具有在硅单晶衬底的主表面上通过气相外延生长的硅外延层，其中所述硅单晶衬底的主表面相对于[100]轴以角度倾斜; 在（011）方向或[0-1-1]方向上，以（100） 在（100）平面的[01-1]方向或[0-11]方向上，角度＆amp; 和角度＆phgr 小于10分钟，硅外延层的掺杂浓度等于或大于1×1019 / cm3。 即使在硅单晶衬底的主表面上形成掺杂浓度为1×1019 / cm3以上的外延层，也抑制了外延层上的条状表面凹凸。