公开(公告)号：US07804375B2

公开(公告)日：2010-09-28

申请号：US11874937

申请日：2007-10-19

申请人： Norio Kobayashi ,  Hideyuki Okabe

发明人： Norio Kobayashi ,  Hideyuki Okabe

IPC分类号： H03C3/00

CPC分类号： H03C3/225

摘要： A modulation circuit is provided that generates an output signal obtained by modulating an input signal with a local signal and includes a local input section that receives the local signal and generates the local signal and an inverted local signal obtained by inverting the local signal, a signal input section that receives the input signal and generates the input signal and an inverted input signal obtained by inverting the input signal, a first multiplying section that outputs from a terminal that receives the input signal a first multiplied signal obtained by multiplying the local signal with the input signal, a second multiplying section that outputs from a terminal that receives the inverted input signal a second multiplied signal obtained by multiplying the inverted local signal with the inverted input signal, an output section that adds the first multiplied signal to the second multiplied signal and generates the output signal, and a transmission line that sends to the output section the first multiplied signal output by the first multiplying section and the second multiplied signal output by the second multiplying section and has an electrical length according to a predetermined frequency as the frequency of the input signal.

摘要翻译： 提供了一种调制电路，其生成通过用本地信号调制输入信号而获得的输出信号，并且包括接收本地信号并产生本地信号的本地输入部分和通过反转本地信号而获得的反相本地信号， 输入部分，其接收输入信号并产生输入信号和通过反相输入信号获得的反相输入信号;第一乘法部分，从接收输入信号的端子输出第一相乘信号，该第一相乘信号通过将本地信号乘以 输入信号，第二乘法部分，从接收反相输入信号的终端输出通过将反相本地信号与反相输入信号相乘而获得的第二相乘信号;将第一相乘信号与第二相乘信号相加的输出部分，以及 产生输出信号和发送到输出端的传输线 取消由第一乘法部分输出的第一相乘信号和由第二乘法部分输出的第二相乘信号，并且具有根据预定频率的电长度作为输入信号的频率。

公开(公告)号：US07516434B2

公开(公告)日：2009-04-07

申请号：US11435759

申请日：2006-05-18

申请人： Hideyuki Okabe

发明人： Hideyuki Okabe

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A computer program product for floorplanning design of a semiconductor integrated circuit, embodied on a computer-readable medium and including code that, when executed, causes a computer to perform the following steps (a) to (d). The step (a) is the step of placing circuit blocks based on a netlist. The step (b) is the step of estimating an interconnection length between two of the placed circuit blocks based on the netlist and positions of the placed circuit blocks. The step (c) is the step of judging whether the estimated interconnection length satisfies timing constraints for connections among the circuit blocks, based on relation data indicating relations among interconnection lengths and timings. The step (d) is the step of outputting the judgment result.

摘要翻译： 一种用于计算机可读介质上体现的半导体集成电路的布局规划设计的计算机程序产品，包括当执行时使计算机执行以下步骤（a）至（d）的代码。 步骤（a）是基于网表放置电路块的步骤。 步骤（b）是基于所述网表和放置的电路块的位置来估计放置在两个电路块之间的互连长度的步骤。 步骤（c）是基于指示互连长度和定时之间的关系的关系数据来判断估计的互连长度是否满足电路块之间的连接的定时约束的步骤。 步骤（d）是输出判断结果的步骤。

公开(公告)号：US20110285435A1

公开(公告)日：2011-11-24

申请号：US13104851

申请日：2011-05-10

申请人： Hideyuki Okabe

发明人： Hideyuki Okabe

IPC分类号： H03L7/06

CPC分类号： H03L7/085

摘要： A VCO oscillates at a frequency that corresponds to a control voltage. A frequency mixer performs frequency mixing of the output signal of the VCO and a local signal having a local frequency. A first filter extracts a difference frequency signal obtained by the mixing operation of the mixer. A phase difference detection unit makes a comparison between the phase of the difference frequency signal extracted by the first filter and the phase of a reference signal having a reference frequency, and generates a phase difference signal that corresponds to the phase difference. A loop filter performs filtering of the phase difference signal so as to generate the control signal. A second filter extracts a summation frequency signal obtained by the mixing operation of the mixer, and outputs the summation frequency signal via an output terminal thereof.

摘要翻译： VCO以对应于控制电压的频率振荡。 混频器执行VCO的输出信号和具有本地频率的本地信号的频率混合。 第一滤波器提取通过混频器的混合操作获得的差频信号。 相位差检测单元对由第一滤波器提取的差频信号的相位与具有参考频率的参考信号的相位进行比较，并产生与相位差对应的相位差信号。 环路滤波器对相位差信号进行滤波，以产生控制信号。 第二滤波器提取通过混频器的混频操作获得的求和频率信号，并通过其输出端输出求和频率信号。

公开(公告)号：US08373461B2

公开(公告)日：2013-02-12

申请号：US13104851

申请日：2011-05-10

申请人： Hideyuki Okabe

发明人： Hideyuki Okabe

IPC分类号： H03L7/06

CPC分类号： H03L7/085

摘要： A VCO oscillates at a frequency that corresponds to a control voltage. A frequency mixer performs frequency mixing of the output signal of the VCO and a local signal having a local frequency. A first filter extracts a difference frequency signal obtained by the mixing operation of the mixer. A phase difference detection unit makes a comparison between the phase of the difference frequency signal extracted by the first filter and the phase of a reference signal having a reference frequency, and generates a phase difference signal that corresponds to the phase difference. A loop filter performs filtering of the phase difference signal so as to generate the control signal. A second filter extracts a summation frequency signal obtained by the mixing operation of the mixer, and outputs the summation frequency signal via an output terminal thereof.

摘要翻译： VCO以对应于控制电压的频率振荡。 混频器执行VCO的输出信号和具有本地频率的本地信号的频率混合。 第一滤波器提取通过混频器的混合操作获得的差频信号。 相位差检测单元对由第一滤波器提取的差频信号的相位与具有参考频率的参考信号的相位进行比较，并产生与相位差对应的相位差信号。 环路滤波器对相位差信号进行滤波，以产生控制信号。 第二滤波器提取通过混频器的混频操作获得的求和频率信号，并通过其输出端输出求和频率信号。

公开(公告)号：US08499268B2

公开(公告)日：2013-07-30

申请号：US13404820

申请日：2012-02-24

申请人： Hideyuki Okabe

发明人： Hideyuki Okabe

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： In a method of supporting a layout design, a net list of an integrated circuit is divided into net lists of clock domain circuit aggregations. A timing constraint is generated to each of the clock domain circuit aggregations. An arrangement order of the clock domain circuit aggregations is determined to satisfy the timing constraint. A layout of the integrated circuit is generated by carrying out arrangement and wiring of the clock domain circuit aggregations based on the arrangement order.

摘要翻译： 在支持布局设计的方法中，集成电路的网络列表被划分为时钟域电路聚合的网络列表。 每个时钟域电路集合产生时序约束。 确定时钟域电路聚合的排列顺序以满足定时约束。 通过根据布置顺序执行时钟域电路集合的布置和布线来生成集成电路的布局。

公开(公告)号：US20070099590A1

公开(公告)日：2007-05-03

申请号：US10596790

申请日：2004-12-16

申请人： Hideyuki Okabe ,  Yuji Kuwana ,  Masayuki Kimishima

发明人： Hideyuki Okabe ,  Yuji Kuwana ,  Masayuki Kimishima

IPC分类号： H04B1/26

CPC分类号： H03D7/1408

摘要： The frequency characteristic of a conversion loss is kept generally constant during conversion of a high frequency received signal into an intermediate frequency signal. There is provided a frequency converter including a balanced balun (10) which branches a locally oscillated signal (Lo) into two signals which have the same amplitude and are different from each other in phase by 180 degrees, low-pass filters (12a, 12b) through which the two signals pass, and antiparallel diode pairs (16a, 16b) which respectively mix outputs from the low-pass filters (12a, 12b) with a high frequency received signal (RF) to produce an intermediate frequency signal (IF) The low-pass filters (12a, 12b) exhibit generally constant impedances in the frequency band of the high frequency received signal (RF). Accordingly, the impedances of the anti-parallel diode pairs (16a, 16b) as viewed from an anti-parallel diode connection point (17) are generally constant in the frequency band of the high frequency received signal (RF), with the result that the frequency characteristic of the conversion loss can be kept generally constant.

摘要翻译： 在将高频接收信号转换成中频信号期间，转换损耗的频率特性保持一般恒定。 提供了一种包括平衡不平衡变换器（10）的频率转换器，其将本地振荡信号（Lo）分成两个相位相同振幅和相互相差180度的信号，低通滤波器（12a， 12b）和两个信号通过的反并联二极管对（16a，16b）分别混合来自低通滤波器（12a，12b）的输出与高频接收信号（RF），以产生 中频信号（IF）低通滤波器（12a，12b）在高频接收信号（RF）的频带中呈现大致恒定的阻抗。 因此，从反并联二极管连接点（17）观察的反并联二极管对（16a，16b）的阻抗在高频接收信号（RF）的频带中通常是恒定的，其中 导致转换损耗的频率特性可以保持一般恒定。

公开(公告)号：US07633353B2

公开(公告)日：2009-12-15

申请号：US11875961

申请日：2007-10-22

申请人： Hideyuki Okabe

发明人： Hideyuki Okabe

IPC分类号： H03H7/42 ,  H01P5/04

CPC分类号： H01P5/10

摘要： A balun circuit is provided that includes a first coupling line in which an unbalanced line thereof is connected to a first terminal and a balanced line thereof is electrically connected to a second terminal, a second coupling line in which an unbalanced line thereof is electrically connected to the unbalanced line of the first coupling line and a balanced line thereof is electrically connected to a third terminal, a first transmission path that is serially connected between the balanced line of the first coupling line and a ground potential, a second transmission path that is serially connected between the balanced line of the second coupling line and a ground potential, and a third transmission path that is serially connected between the unbalanced line of the first coupling line and the unbalanced line of the second coupling line. These transmission lines are formed such that an amplitude characteristic of S12 is the same as an amplitude characteristic of S13 and a phase characteristic of S12 is inverted in relation to a phase characteristic of S13.

摘要翻译： 提供了一种平衡 - 不平衡转换电路，其包括第一耦合线，其中不平衡线连接到第一端子，并且其平衡线电连接到第二端子，第二耦合线，其不平衡线电连接到 第一耦合线的不平衡线及其平衡线电连接到第三端子，串联连接在第一耦合线路的平衡线路和接地电位之间的第一传输路径，串联的第二传输路径 连接在第二耦合线的平衡线和地电位之间，以及第三传输路径，其串联连接在第一耦合线的不平衡线与第二耦合线的不平衡线之间。 这些传输线形成为使得S12的振幅特性与S13的振幅特性相同，并且S12的相位特性相对于S13的相位特性反转。

公开(公告)号：US20060265678A1

公开(公告)日：2006-11-23

申请号：US11435759

申请日：2006-05-18

申请人： Hideyuki Okabe

发明人： Hideyuki Okabe

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A computer program product for floorplanning design of a semiconductor integrated circuit, embodied on a computer-readable medium and including code that, when executed, causes a computer to perform the following steps (a) to (d). The step (a) is the step of placing circuit blocks based on a netlist. The step (b) is the step of estimating an interconnection length between two of the placed circuit blocks based on the netlist and positions of the placed circuit blocks. The step (c) is the step of judging whether the estimated interconnection length satisfies timing constraints for connections among the circuit blocks, based on relation data indicating relations among interconnection lengths and timings. The step (d) is the step of outputting the judgment result.

公开(公告)号：US20060117283A1

公开(公告)日：2006-06-01

申请号：US11283693

申请日：2005-11-22

申请人： Tetsuya Katou ,  Makoto Nonaka ,  Hideyuki Okabe ,  Kazuhisa Shimazu

发明人： Tetsuya Katou ,  Makoto Nonaka ,  Hideyuki Okabe ,  Kazuhisa Shimazu

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5081 ,  G06F17/5022

摘要： A verification method of an integrated circuit including an input/output buffer placed in a periphery of a semiconductor device and an internal circuit. The verification method stores physical information on routing of the input/output buffer into a library of the input/output buffer and verifies a placement of the input/output buffer based on the physical information.

摘要翻译： 一种集成电路的验证方法，包括放置在半导体器件周围的输入/输出缓冲器和内部电路。 验证方法将输入/输出缓冲器路由的物理信息存储到输入/输出缓冲器的库中，并根据物理信息验证输入/输出缓冲器的位置。