公开(公告)号：US5235538A

公开(公告)日：1993-08-10

申请号：US756884

申请日：1991-09-09

申请人： Norio Sumi ,  Hirotsugu Kojima ,  Junko Nakase

发明人： Norio Sumi ,  Hirotsugu Kojima ,  Junko Nakase

IPC分类号： G06F7/52 ,  G06F7/53 ,  G06F7/533

CPC分类号： G06F7/5332 ,  G06F7/523

摘要： The present invention features performance of operation processing between a signal obtained by converting a coefficient into a Booth code with a Booth encoder, storing the Booth code in a memory device in advance and reading out the stored Booth code for processing an input signal in a semiconductor operation device or a digital filter. As a result, a coding operation by a Booth encoder of the present invention will be performed only once at the time of rewriting a coefficient and will not be repeated, thereby enabling a high-speed operation and realizing reduction of circuit scale at the same time by using an encoded Booth code directly in an operation after a coefficient has been determined.

摘要翻译： 本发明的特征在于，将通过将系数转换为布斯编码而得到的信号与布斯编码器之间的操作处理的性能，将布斯代码预先存储在存储装置中，并读出存储的布斯码，以处理半导体中的输入信号 操作装置或数字滤波器。 结果，本发明的布斯编码器的编码操作在重写系数时将仅执行一次，并且不会重复，从而能够高速操作并同时实现电路规模的降低 通过在确定系数之后的操作中直接使用经编码的布斯代码。

公开(公告)号：US5222035A

公开(公告)日：1993-06-22

申请号：US706389

申请日：1991-05-28

申请人： Junko Nakase ,  Hirotsugu Kojima

发明人： Junko Nakase ,  Hirotsugu Kojima

IPC分类号： H03H17/00 ,  H03H17/02 ,  H03H17/06

CPC分类号： H03H17/0286 ,  H03H17/06

摘要： When each sample is expressed by digital signals of 8 bits, 8 bits constituting each of the digital signals are divided into data of upper 5 bits including the most significant bit, and data of lower 4 bits including the least significant bit. These two data are respectively inputted to two filter circuit units, and are simultaneously subjected to a filtering process separately. Outputs of these two filter circuit units are inputted to an adder. In the adder, the output of the filter circuit unit being data of upper 5 bits subjected to a filtering process is weighted by a factor of 2 to the 4th power, and the weighted output is added to the output of the other filter circuit unit. The results of adding are outputted from the adder as signals obtained by the original digital signals of 8 bits subjected to the filtering process. Since the number of bits of individual data is made small by the division, the operation speed of computing elements and the number of times of recursive or multiple uses of computing elements are increased so that the circuit scale of the entire filter circuit can be reduced.

摘要翻译： 当每个采样由8位的数字信号表示时，构成每个数字信号的8位被分成包括最高有效位的高5位的数据和包括最低有效位的低4位的数据。 这两个数据分别输入到两个滤波电路单元，并分别同时进行滤波处理。 这两个滤波器电路单元的输出被输入到加法器。 在加法器中，作为经过滤波处理的高5位的数据的滤波器电路单元的输出被加权为2倍至4倍，加权输出相加于另一个滤波电路单元的输出。 从作为滤波处理的8位的原始数字信号得到的信号，从加法器输出相加结果。 由于通过除法使个别数据的位数变小，所以计算单元的运算速度和运算单元的递归或多次使用次数增加，从而可以减小整个滤波电路的电路规模。

公开(公告)号：US5742361A

公开(公告)日：1998-04-21

申请号：US753761

申请日：1996-11-29

申请人： Junko Nakase ,  Yukio Fujii ,  Hiroshi Gunji ,  Katsumi Matsuno

发明人： Junko Nakase ,  Yukio Fujii ,  Hiroshi Gunji ,  Katsumi Matsuno

IPC分类号： H04N21/236 ,  H04N21/2368 ,  H04N21/434 ,  H04N7/24

CPC分类号： H04N21/8547 ,  H04N21/434 ,  H04N21/4345 ,  H04N21/44016

摘要： A data demultiplexer includes a write controller, a memory, an analyzing processing unit, and transfer control units. The write controller writes packets which have arrived thereat into the memory in the order of arrival and sends the write information to the analyzing processing unit. The analyzing processing unit analyzes packets in the order of arrival on the basis of the write information and sends only the result of analysis to the transfer control units. On the basis of the result of analysis, the transfer control units send data read from the memory in the order of packet arrival to the decoder. A data demultiplexer capable of reducing the processing in the analyzing processing unit can be provided.

摘要翻译： 数据解复用器包括写入控制器，存储器，分析处理单元和传送控制单元。 写入控制器按照到达顺序将到达的数据包写入到存储器中，并将写入信息发送到分析处理单元。 分析处理单元基于写入信息按照到达顺序分析分组，并且仅将分析结果发送到传送控制单元。 基于分析结果，传送控制单元按照分组到达解码器的顺序从存储器读出数据。 可以提供能够减少分析处理单元中的处理的数据解复用器。

公开(公告)号：US06675183B2

公开(公告)日：2004-01-06

申请号：US10046983

申请日：2002-01-17

申请人： Junko Nakase ,  Takashi Nakamoto

发明人： Junko Nakase ,  Takashi Nakamoto

IPC分类号： G06F1710

CPC分类号： H03H17/0202 ,  H04N9/64

摘要： There is provided a filtering circuit whose circuit scale is small and which is suitable for a digital data string in which data of luminance signals Y and color-difference signals Cb and Cr are regularly inserted or multiplexed. The digital filtering circuit comprises a delay line composed of a plurality of D flip-flops which is operative with frequency of the data string in which the luminance signals Y and the color-difference signals Cb and Cr are regularly inserted or multiplexed a plurality of multipliers for multiplying a plurality of taps of the delay line by respective coefficients and an adder for adding outputs of said multipliers, wherein the taps connected to the multipliers is switched by selectors. It allows one digital filtering circuit to be used for processing the signals Y, Cb and Cr in a time division manner to realize the digital filtering circuit which uses less multipliers and adders and whose circuit scale is small.

摘要翻译： 提供了一种滤波电路，其电路规模小，适用于其中定期插入或复用亮度信号Y和色差信号Cb和Cr的数据的数字数据串。 数字滤波电路包括由多个D触发器组成的延迟线，该D触发器与数据串的频率一起工作，其中亮度信号Y和色差信号Cb和Cr被有规律地插入或多路复用多个乘法器 用于将所述延迟线的多个抽头乘以相应的系数;以及加法器，用于相加所述乘法器的输出，其中连接到乘法器的抽头由选择器切换。 它允许一个数字滤波电路以时分方式用于处理信号Y，Cb和Cr，以实现使用较少乘法器和加法器并且其电路规模小的数字滤波电路。

公开(公告)号：US06377968B1

公开(公告)日：2002-04-23

申请号：US09291956

申请日：1999-04-15

申请人： Junko Nakase ,  Takashi Nakamoto

发明人： Junko Nakase ,  Takashi Nakamoto

IPC分类号： G06F1710

CPC分类号： H03H17/0202 ,  H04N9/64

摘要： There is provided a filtering circuit whose circuit scale is small and which is suitable for a digital data string in which data of luminance signals Y and color-difference signals Cb and Cr are regularly inserted or multiplexed. The digital filtering circuit includes a delay line composed of a plurality of D flip-flops which is operative with frequency of the data string in which the luminance signals Y and the color-difference signals Cb and Cr are regularly inserted or multiplexed a plurality of multipliers for multiplying a plurality of taps of the delay line by respective coefficients and an adder for adding outputs of said multipliers, wherein the taps connected to the multipliers is switched by selectors. It allows one digital filtering circuit to be used for processing the signals Y, Cb and Cr in a time division manner to realize the digital filtering circuit which uses less multipliers and adders and whose circuit scale is small.

摘要翻译： 提供了一种滤波电路，其电路规模小，适用于其中定期插入或复用亮度信号Y和色差信号Cb和Cr的数据的数字数据串。 数字滤波电路包括由多个D触发器组成的延迟线，该D触发器与数据串的频率一起工作，其中亮度信号Y和色差信号Cb和Cr被有规律地插入或复用为多个乘法器 用于将所述延迟线的多个抽头乘以相应的系数;以及加法器，用于相加所述乘法器的输出，其中连接到乘法器的抽头由选择器切换。 它允许使用一个数字滤波电路来以时分方式处理信号Y，Cb和Cr，以实现使用较少乘法器和加法器并且其电路规模小的数字滤波电路。

公开(公告)号：US5438577A

公开(公告)日：1995-08-01

申请号：US868708

申请日：1992-04-15

申请人： Junko Nakase ,  Nobukazu Doi

发明人： Junko Nakase ,  Nobukazu Doi

IPC分类号： H03M13/00 ,  H03M13/15 ,  H03M13/33 ,  H04L1/00 ,  H04N19/00 ,  H04N19/102 ,  H04N19/146 ,  H04N19/423 ,  H04N19/65 ,  H04N19/67 ,  H04N19/85 ,  G06F11/10

CPC分类号： H03M13/151 ,  H03M13/00 ,  H03M13/33

摘要： An error correcting system for performing error correction for error codewords received sequentially in a codeword string on a pipeline processing basis. The system comprises a processing block for generating syndrome data on the basis of parity symbols of each of the codewords, a processing block for performing logical processing operation to derive error locations and error values on the basis of the syndrome data, and a processing block for performing correcting operation for delayed codewords based on the error locations and values. These three processing blocks start their processing operation when receiving individual control signals based on reset signals indicative of leading heads of the respective codewords in the string and delayed by mutually different delay times. With regard to incomplete ones of the codewords that are shorter than a right correct codeword length, the logical processing operation for the error location and error evaluation as well as the error correcting operation is inhibited.

摘要翻译： 一种错误校正系统，用于对在流水线处理基础上的码字串中顺序地接收的错误代码进行纠错。 该系统包括用于基于每个码字的奇偶校验符号产生校正子数据的处理块，用于执行基于校正子数据导出误差位置和误差值的逻辑处理操作的处理块，以及用于 基于错误位置和值对延迟码字执行校正操作。 当基于指示字符串中各个码字的前导头的复位信号接收各个控制信号时，这三个处理块开始其处理操作，并被相互不同的延迟时间延迟。 关于短于正确的码字长度的不完整的码字，抑制了错误位置和错误评估的逻辑处理操作以及纠错操作。