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公开(公告)号：US20110113208A1
公开(公告)日：2011-05-12
申请号：US12989981
申请日：2008-05-01
CPC分类号： G06F11/1438 , G06F11/1482 , G06F11/203 , G06F11/2046
摘要： Methods and systems for storing checkpoint data in non-volatile memory are described. According to one embodiment, a data storage method includes executing an application using processing circuitry and during the execution, writing data generated by the execution of the application to volatile memory. An indication of a checkpoint is provided after writing the data. After the indication has been provided, the method includes copying the data from the volatile memory to non-volatile memory and, after the copying, continuing the execution of the application. The method may include suspending execution of the application. According to another embodiment, a data storage method includes receiving an indication of a checkpoint associated with execution of one or more applications and, responsive to the receipt, initiating copying of data resulting from execution of the one or more applications from volatile memory to non-volatile memory. In some embodiments, the non-volatile memory may be solid-state non-volatile memory.
摘要翻译： 描述了用于在非易失性存储器中存储检查点数据的方法和系统。 根据一个实施例，数据存储方法包括使用处理电路执行应用，并且在执行期间，将由应用执行产生的数据写入易失性存储器。 写入数据后提供检查点的指示。 在提供指示之后，该方法包括将数据从易失性存储器复制到非易失性存储器，并且在复制之后继续执行应用程序。 该方法可以包括暂停应用程序的执行。 根据另一个实施例，数据存储方法包括接收与一个或多个应用的执行相关联的检查点的指示，并且响应于该接收，开始将由一个或多个应用执行所产生的数据从易失性存储器复制到非易失性存储器， 易失性存储器 在一些实施例中，非易失性存储器可以是固态非易失性存储器。
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2.发明授权公开(公告)号：US08037350B1
公开(公告)日：2011-10-11
申请号：US12250367
申请日：2008-10-13
IPC分类号： G06F11/00
CPC分类号： G06F11/1641 , G06F11/1497 , G06F11/165 , G06F11/1658 , G06F11/184
摘要： Processor operating methods and integrated circuits are described. According to one embodiment, a processor operating method includes executing an application using a first number of a plurality of processor cores. The method also includes, during the executing using the first number, evaluating a transition criterion and after the evaluating, executing the application using a second number of the plurality of processor cores. According to another embodiment, an integrated circuit includes a plurality of processor cores and processing circuitry. The processing circuitry is configured to configure a first number of the plurality of processor cores to execute an application, evaluate a transition criterion, and, in response to evaluating the transition criterion, configure a second number of the plurality of processor cores to execute the application. Additional embodiments are described in the disclosure.
摘要翻译： 描述处理器操作方法和集成电路。 根据一个实施例，处理器操作方法包括使用第一数量的多个处理器核来执行应用。 该方法还包括在使用第一个数字的执行期间评估转换标准，并且在评估之后，使用多个处理器核心的第二数量来执行应用程序。 根据另一个实施例，集成电路包括多个处理器核心和处理电路。 处理电路被配置为配置多个处理器核的第一数量以执行应用，评估转换标准，并且响应于评估转换标准，配置多个处理器核的第二数量以执行应用 。 在本公开中描述了另外的实施例。
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公开(公告)号：US07941698B1
公开(公告)日：2011-05-10
申请号：US12252144
申请日：2008-10-15
IPC分类号： G06F11/00
CPC分类号： G06F11/1641 , G06F11/1471 , G06F11/1497 , G06F11/1675 , G06F11/184 , G06F2201/805 , G06F2201/81 , G06F2201/845
摘要： Processor operating methods and integrated circuits are described. According to one embodiment, an integrated circuit includes a processor configured to execute a first application and to redundantly execute a second application while executing the first application, the first application being different from the second application. According to another embodiment, a processor operating method includes receiving a request to execute an application using a processor having a plurality of processor cores. The method also includes, in response to the receiving, determining whether the application should be executed redundantly or non-redundantly, non-redundantly executing the application using one processor core of the plurality if the determining comprises determining that the application should be executed non-redundantly, and redundantly executing the application using two or more processor cores of the plurality if the determining comprises determining that the application should be executed redundantly.
摘要翻译： 描述处理器操作方法和集成电路。 根据一个实施例，集成电路包括被配置为执行第一应用并且在执行第一应用时冗余地执行第二应用的处理器，所述第一应用与第二应用不同。 根据另一个实施例，处理器操作方法包括使用具有多个处理器核的处理器来接收执行应用的请求。 所述方法还包括：响应于所述接收，确定所述应用是否应该被冗余地执行或非冗余地执行，如果所述确定包括确定所述应用应该被执行，则非冗余地执行所述应用的多个处理器核心， 冗余地并冗余地执行应用程序，如果确定包括确定该应用程序应该被冗余执行，则使用多个的两个或多个处理器核心。
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4.发明授权Reconfiguration in a multi-core processor system with configurable isolation 有权在具有可配置隔离的多核处理器系统中重新配置公开(公告)号：US07966519B1
公开(公告)日：2011-06-21
申请号：US12250381
申请日：2008-10-13
IPC分类号： G06F11/00
CPC分类号： G06F11/1423 , G06F11/2035
摘要： Methods and integrated circuits for reconfiguration in a multi-core processor system with configurable isolation are described. According to one embodiment, a processor configuration method includes determining that a first module is faulty. A second module is configured to communicate with the first module when the first module is not faulty. The method also includes analyzing a third module with respect to a substitution criterion, selecting the third module based on the analyzing determining that the third module satisfies the substitution criterion, and subsequent to the selecting, configuring the second module to communicate with the third module instead of the first module. Additional embodiments are described in the disclosure.
摘要翻译： 描述了具有可配置隔离的多核处理器系统中用于重新配置的方法和集成电路。 根据一个实施例，处理器配置方法包括确定第一模块是有故障的。 第二模块被配置为当第一模块没有故障时与第一模块通信。 该方法还包括相对于替代标准分析第三模块，基于分析确定第三模块满足替代标准来选择第三模块，并且在选择之后，配置第二模块以与第三模块通信 的第一个模块。 在本公开中描述了另外的实施例。
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公开(公告)号：US08151122B1
公开(公告)日：2012-04-03
申请号：US11773759
申请日：2007-07-05
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： In a method for managing power budgets among a plurality of electronic components having respective power budgets, at least part of the power budget of an electronic component that has failed is dynamically re-allocated to at least one of the other plurality of electronic components, to thereby increase performance of the plurality of electronic components.
摘要翻译： 在用于管理具有各自的功率预算的多个电子部件中的功率预算的方法中，已经故障的电子部件的功率预算的至少一部分被动态地重新分配给其他多个电子部件中的至少一个， 从而增加了多个电子部件的性能。
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公开(公告)号：US07743285B1
公开(公告)日：2010-06-22
申请号：US11787881
申请日：2007-04-17
IPC分类号： G06F11/00
CPC分类号： G06F11/1658 , G06F11/1641 , G06F11/165 , G06F11/1666 , G06F11/181 , G06F11/184 , G06F11/2017
摘要： One embodiment relates to a high-availability computation apparatus including a chip multiprocessor. Multiple fault zones are configurable in the chip multiprocessor, each fault zone being logically independent from other fault zones. Comparison circuitry is configured to compare outputs from redundant processes run in parallel on the multiple fault zones. Another embodiment relates to a method of operating a high-availability system using a chip multiprocessor. A redundant computation is performed in parallel on multiple fault zones of the chip multiprocessor and outputs from the multiple fault zones are compared. When a miscompare is detected, an error recovery process is performed. Other embodiments, aspects and features are also disclosed.
摘要翻译： 一个实施例涉及包括码片多处理器的高可用性计算装置。 多个故障区域可在芯片多处理器中配置，每个故障区域在逻辑上与其他故障区域无关。 比较电路配置为比较多个故障区并行运行的冗余过程的输出。 另一实施例涉及使用码片多处理器来操作高可用性系统的方法。 对多芯片多处理器的多个故障区并行执行冗余计算，并比较多个故障区域的输出。 当检测到错误比较时，执行错误恢复处理。 还公开了其它实施例，方面和特征。
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