公开(公告)号：US10256967B2

公开(公告)日：2019-04-09

申请号：US15863983

申请日：2018-01-08

Applicant: Novatek Microelectronics Corp.

Inventor： Chang-Cheng Huang ,  Shen-Iuan Liu ,  Ju-Lin Huang ,  Tzu-Chien Tzeng ,  Keko-Chun Liang ,  Yu-Hsiang Wang ,  Che-Wei Yeh

IPC: H04L7/00 ,  H03L7/08 ,  H03L7/091 ,  H03L7/093 ,  H03L7/089

Abstract: A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.

公开(公告)号：US20180198597A1

公开(公告)日：2018-07-12

申请号：US15863983

申请日：2018-01-08

Applicant: Novatek Microelectronics Corp.

Inventor： Chang-Cheng Huang ,  Shen-Iuan Liu ,  Ju-Lin Huang ,  Tzu-Chien Tzeng ,  Keko-Chun Liang ,  Yu-Hsiang Wang ,  Che-Wei Yeh

IPC: H04L7/00 ,  H03L7/08 ,  H03L7/089 ,  H03L7/093 ,  H03L7/091

CPC classification number: H04L7/0016 ,  H03L7/0807 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/0898 ,  H03L7/091 ,  H03L7/093 ,  H03L2207/06

Abstract: A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.