公开(公告)号：US09640249B2

公开(公告)日：2017-05-02

申请号：US14282809

申请日：2014-05-20

Applicant: Nvidia Corporation

Inventor： Gang Chen ,  Jing Guo ,  Jun Yang

IPC: G11C11/00 ,  G11C11/419 ,  G11C5/14

CPC classification number: G11C11/419 ,  G11C5/147

Abstract: A write-assist memory includes a memory supply voltage and a column of SRAM cells that is controlled by a pair of bit lines, during a write operation. Additionally, the write-assist memory includes a write-assist unit that is coupled to the memory supply voltage and the column of SRAM cells and has a separable conductive line located between the pair of bit lines that provides a collapsible SRAM supply voltage to the column of SRAM cells based on a capacitive coupling of a control signal in the pair of bit lines, during the write operation. A method of operating a write-assist memory is also provided.

公开(公告)号：US20150235695A1

公开(公告)日：2015-08-20

申请号：US14282809

申请日：2014-05-20

Applicant: Nvidia Corporation

Inventor： Gang Chen ,  Jing Guo ,  Jun Yang

IPC: G11C11/419 ,  G11C5/14

CPC classification number: G11C11/419 ,  G11C5/147

Abstract: A write-assist memory includes a memory supply voltage and a column of SRAM cells that is controlled by a pair of bit lines, during a write operation. Additionally, the write-assist memory includes a write-assist unit that is coupled to the memory supply voltage and the column of SRAM cells and has a separable conductive line located between the pair of bit lines that provides a collapsible SRAM supply voltage to the column of SRAM cells based on a capacitive coupling of a control signal in the pair of bit lines, during the write operation. A method of operating a write-assist memory is also provided.

Abstract translation: 在写操作期间，写辅助存储器包括由一对位线控制的存储器电源电压和一列SRAM单元。 另外，写辅助存储器包括写辅助单元，其耦合到存储器电源电压和SRAM单元列，并且具有位于该对位线之间的可分离导线，该可分离导线向列提供可折叠的SRAM供电电压 在写操作期间基于位线对中的控制信号的电容耦合的SRAM单元。 还提供了一种操作写辅助存储器的方法。

公开(公告)号：US20150235681A1

公开(公告)日：2015-08-20

申请号：US14279796

申请日：2014-05-16

Applicant: Nvidia Corporation

Inventor： Gang Chen ,  Jing Guo ,  Yiqi Wang ,  Hwong-Kwo Lin

IPC: G11C7/12

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412

Abstract: A memory read system includes a memory column having a plurality of dual port memory cells that are controlled by separate read word lines and a read bit line structure organized into upper and lower read bit line portions. Additionally, the memory read system also includes a pseudo-differential memory read unit coupled to the read bit line structure, wherein the upper and lower read bit line portions respectively control corresponding upper and lower local bit lines to provide a global bit line for the memory column. A method of reading a memory is also included.

Abstract translation: 存储器读取系统包括具有多个双端口存储器单元的存储器列，该多个双端口存储器单元由分离的读取字线和被组织为上部和下部读取位线部分的读取位线结构控制。 此外，存储器读取系统还包括耦合到读取位线结构的伪差分存储器读取单元，其中上部和下部读取位线部分分别控制相应的上部和下部本地位线，以提供用于存储器的全局位线 柱。 还包括读取存储器的方法。