公开(公告)号：US20150235681A1

公开(公告)日：2015-08-20

申请号：US14279796

申请日：2014-05-16

Applicant: Nvidia Corporation

Inventor： Gang Chen ,  Jing Guo ,  Yiqi Wang ,  Hwong-Kwo Lin

IPC: G11C7/12

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412

Abstract: A memory read system includes a memory column having a plurality of dual port memory cells that are controlled by separate read word lines and a read bit line structure organized into upper and lower read bit line portions. Additionally, the memory read system also includes a pseudo-differential memory read unit coupled to the read bit line structure, wherein the upper and lower read bit line portions respectively control corresponding upper and lower local bit lines to provide a global bit line for the memory column. A method of reading a memory is also included.

Abstract translation: 存储器读取系统包括具有多个双端口存储器单元的存储器列，该多个双端口存储器单元由分离的读取字线和被组织为上部和下部读取位线部分的读取位线结构控制。 此外，存储器读取系统还包括耦合到读取位线结构的伪差分存储器读取单元，其中上部和下部读取位线部分分别控制相应的上部和下部本地位线，以提供用于存储器的全局位线 柱。 还包括读取存储器的方法。