公开(公告)号：US10200022B2

公开(公告)日：2019-02-05

申请号：US15620594

申请日：2017-06-12

Applicant: Nvidia Corporation

Inventor： Sanjay Pant ,  Tezaswi Raja ,  Andy Charnas

IPC: G06F1/26 ,  H03K7/06 ,  H03L7/06 ,  H03K5/14 ,  H03K7/08 ,  G06F1/04 ,  H03K5/00

Abstract: A method for regulating voltage for a processor is disclosed. The method comprises requesting a target frequency value, wherein the target frequency value determines a target clock frequency for clocking the processor. The method also comprises comparing the target clock frequency to a first signal to generate an error signal. Further, the method comprises using the error signal to generate a duty cycle control signal, wherein the duty cycle control signal is operable to generate a periodic waveform. Finally, the method comprises generating an output regulator voltage using the periodic waveform, wherein the output voltage is operable to provide power to the processor.

公开(公告)号：US10103719B2

公开(公告)日：2018-10-16

申请号：US14856191

申请日：2015-09-16

Applicant: Nvidia Corporation

Inventor： Sanjay Pant ,  Tezaswi Raja ,  Andy Charnas

IPC: G06F1/26 ,  H03K7/06 ,  H03L7/06 ,  H03K5/14 ,  H03K7/08 ,  G06F1/04 ,  H03K5/00

Abstract: A method for regulating voltage for a processor is disclosed. The method comprises requesting a target frequency value, wherein the target frequency value determines a target clock frequency for clocking the processor. The method also comprises comparing the target clock frequency to a first signal to generate an error signal. Further, the method comprises using the error signal to generate a duty cycle control signal, wherein the duty cycle control signal is operable to generate a periodic waveform. Finally, the method comprises generating an output regulator voltage using the periodic waveform, wherein the output voltage is operable to provide power to the processor.