公开(公告)号：US11880261B2

公开(公告)日：2024-01-23

申请号：US17709720

申请日：2022-03-31

Applicant: Nvidia Corporation

Inventor： Evgeny Bolotin ,  Yaosheng Fu ,  Zi Yan ,  Gal Dalal ,  Shie Mannor ,  David Nellans

IPC: G06F1/324 ,  G06F11/34 ,  G06F1/20

CPC classification number: G06F1/324 ,  G06F1/206 ,  G06F11/3495

Abstract: A system, method, and apparatus of power management for computing systems are included herein that optimize individual frequencies of components of the computing systems using machine learning. The computing systems can be tightly integrated systems that consider an overall operating budget that is shared between the components of the computing system while adjusting the frequencies of the individual components. An example of an automated method of power management includes: (1) learning, using a power management (PM) agent, frequency settings for different components of a computing system during execution of a repetitive application, and (2) adjusting the frequency settings of the different components using the PM agent, wherein the adjusting is based on the repetitive application and one or more limitations corresponding to a shared operating budget for the computing system.

公开(公告)号：US20230079978A1

公开(公告)日：2023-03-16

申请号：US17709720

申请日：2022-03-31

Applicant: Nvidia Corporation

Inventor： Evgeny Bolotin ,  Yaosheng Fu ,  Zi Yan ,  Gal Dalal ,  Shie Mannor ,  David Nellans

IPC: G06F1/324 ,  G06F1/20 ,  G06F11/34

Abstract: A system, method, and apparatus of power management for computing systems are included herein that optimize individual frequencies of components of the computing systems using machine learning. The computing systems can be tightly integrated systems that consider an overall operating budget that is shared between the components of the computing system while adjusting the frequencies of the individual components. An example of an automated method of power management includes: (1) learning, using a power management (PM) agent, frequency settings for different components of a computing system during execution of a repetitive application, and (2) adjusting the frequency settings of the different components using the PM agent, wherein the adjusting is based on the repetitive application and one or more limitations corresponding to a shared operating budget for the computing system.

公开(公告)号：US12130750B2

公开(公告)日：2024-10-29

申请号：US18118020

申请日：2023-03-06

Applicant: NVIDIA Corporation

Inventor： Aninda Manocha ,  Zi Yan ,  David Nellans

IPC: G06F12/1027

CPC classification number: G06F12/1027

Abstract: Computer systems often employ virtual address translation hierarchies in which virtual memory addresses are mapped to physical memory. Use of the virtual address translation hierarchy speeds up the virtual address translation when the required mapping is stored in one of the higher levels of the hierarchy. To reduce a number of misses occurring in the virtual address translation hierarchy, huge memory pages may be selectively employed, which map larger continuous regions of virtual memory to continuous regions of physical memory, thereby increasing the coverage of each entry in the virtual address translation hierarchy. The present disclosure provides hardware support for optimizing this huge memory page selection.

公开(公告)号：US20240303201A1

公开(公告)日：2024-09-12

申请号：US18118020

申请日：2023-03-06

Applicant: NVIDIA Corporation

Inventor： Aninda Manocha ,  Zi Yan ,  David Nellans

IPC: G06F12/1027

CPC classification number: G06F12/1027

Abstract: Computer systems often employ virtual address translation hierarchies in which virtual memory addresses are mapped to physical memory. Use of the virtual address translation hierarchy speeds up the virtual address translation when the required mapping is stored in one of the higher levels of the hierarchy. To reduce a number of misses occurring in the virtual address translation hierarchy, huge memory pages may be selectively employed, which map larger continuous regions of virtual memory to continuous regions of physical memory, thereby increasing the coverage of each entry in the virtual address translation hierarchy. The present disclosure provides hardware support for optimizing this huge memory page selection.