公开(公告)号：US20180255255A1

公开(公告)日：2018-09-06

申请号：US15446711

申请日：2017-03-01

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Yingkan Lin ,  Tiejun Dai ,  Cheng-Pin Lin ,  Yu-Shen Yang

IPC: H04N5/357 ,  H04N5/376 ,  H04N5/907 ,  H04N5/378

CPC classification number: H04N5/3577 ,  H04N5/3765 ,  H04N5/378 ,  H04N5/907

Abstract: Methods and apparatuses for data transmission in an image sensor are disclosed herein. An example data transmission circuit may include a plurality of transmission banks coupled in series with a first one of the plurality of transmission banks coupled to function logic, where each of the plurality of transmission banks are coupled to provide image data to a subsequent transmission bank in a direction toward the function logic in response to a clock signal, a plurality of delays coupled in series, wherein each of the plurality of delays is associated with and coupled to a respective transmission bank of the plurality of transmission banks, and wherein the clock signal is received by each of the plurality of transmission banks after being delayed by a respective number of delays of the plurality of delays in relation to the function logic.

公开(公告)号：US10110837B2

公开(公告)日：2018-10-23

申请号：US15446711

申请日：2017-03-01

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Yingkan Lin ,  Tiejun Dai ,  Cheng-Pin Lin ,  Yu-Shen Yang

IPC: H04N5/357 ,  H04N5/376 ,  H04N5/907 ,  H04N5/378

Abstract: Methods and apparatuses for data transmission in an image sensor are disclosed herein. An example data transmission circuit may include a plurality of transmission banks coupled in series with a first one of the plurality of transmission banks coupled to function logic, where each of the plurality of transmission banks are coupled to provide image data to a subsequent transmission bank in a direction toward the function logic in response to a clock signal, a plurality of delays coupled in series, wherein each of the plurality of delays is associated with and coupled to a respective transmission bank of the plurality of transmission banks, and wherein the clock signal is received by each of the plurality of transmission banks after being delayed by a respective number of delays of the plurality of delays in relation to the function logic.