公开(公告)号：US11431939B1

公开(公告)日：2022-08-30

申请号：US17217935

申请日：2021-03-30

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Lihang Fan ,  Nijun Jiang ,  Liang Zuo ,  Yuedan Li ,  Min Qu

IPC: H04N5/378 ,  H03M1/18 ,  H04N5/357 ,  H03M1/12 ,  H03M3/00

Abstract: A clock control circuit of an ADC includes a plurality of fractional divider circuits, each including a programmable integer divider coupled to receive an enable skew signal, a clock signal, and an output integer signal to divide down the clock signal by a factor responsive to the output integer signal to generate a fractional divider signal. A delta-sigma modulator is coupled to receive a fractional modulus signal, an input integer signal, and the fractional divider signal to generate the output integer signal, which is a varying signal each cycle and having a long term average DC value substantially equal to a fractional divider ratio K. An extended gain control circuit is coupled to receive the fractional divider signal from each of the fractional divider circuits to generate a plurality of ramp clock signals with adjustable frequencies to adjust a gain setting of a ramp generator of the ADC.