-
1.发明授权Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources 失效用于配置具有可变粒度组件的FPGA以提供对互连资源的时间共享访问的方法
公开(公告)号：US6124730A
公开(公告)日：2000-09-26
申请号：US212022
申请日：1998-12-15
IPC分类号： H03K19/173 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17748 , H03K19/1737 , H03K19/17736 , H03K19/17756 , H03K19/1778
摘要： A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions. Each CBE may be programmably configured to provide no more than a 2-to-1 dynamic multiplexer (2:1 DyMUX). The dynamically-selectable output of such a synthesized 2:1 DyMUX may then be output onto a shared interconnect line. Pairs of CBE's may be synthetically combined to efficiently define 4:1 DyMUX's with each such 4:1 multiplexer occupying a Configurable Building Block (CBB) structure. Pairs of CBB's may be synthetically combined to efficiently define 8:1 DyMUX's with each such synthesized 8:1 multiplexer occupying a vertically or horizontally-extending leg portion of an L-shaped, VGB structure (Variable Grain Block). The so-configured leg portion of the VGB may then output the signal selected by its 8:1 DyMUX onto a shared interconnect line that is drivable by the VGB leg. Pairs or quartets of VGB's may be synthetically combined to efficiently define higher order, N:1 DyMUX's.
摘要翻译： 可变格式架构（VGA）用于从原始构建元素（CBE）合成每个给定任务的适当量的动态复用能力。 这些可配置构建单元（CBE）中的未使用的组合被重新配置以执行进一步的逻辑功能来代替动态复用功能。 每个CBE可以可编程地配置为提供不超过2对1的动态多路复用器（2：1 DyMUX）。 然后可以将这种合成的2:1 DyMUX的动态可选输出输出到共享互连线上。 CBE的对可以合成，以有效地定义4：1的DyMUX，每个这样的4：1多路复用器占用可配置的构建块（CBB）结构。 CBB的对可以合成组合，以有效地定义8：1 DyMUX，每个这样合成的8：1多路复用器占据L形VGB结构（可变颗粒块）的垂直或水平延伸的腿部分。 然后，VGB的如此配置的腿部分可以将由其8：1 DyMUX选择的信号输出到由VGB支路驱动的共享互连线上。 VGB的对或四重组可以合成组合，以有效地定义高阶N：1 DyMUX。
-
公开(公告)号：US6097212A
公开(公告)日：2000-08-01
申请号：US948306
申请日：1997-10-09
IPC分类号： H03K19/173 , H03K19/177 , H01L25/00
CPC分类号： H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17748 , H03K19/17752 , H03K19/17756 , H03K19/17792 , H03K19/17796 , H01L2924/0002
摘要： A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB's) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUT's) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUT's and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions. Each VGB has a common controls section, a wide-gating section and a carry-propagating section. Each super-VGB has a centrally-shared section of longline drivers that may be accessed from any of the constituent VGB's. A diversified spectrum of interconnect lines, including 2xL, 4xL, 8xL and direct connect surround each super-VGB to provide different kinds of interconnect.
-
3.发明授权Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources 有权用于配置具有可变粒度块和共享逻辑的FPGA的方法，用于将结果输出的对称路由提供给不同方向和可三态互连资源公开(公告)号：US06204686B1
公开(公告)日：2001-03-20
申请号：US09216662
申请日：1998-12-16
IPC分类号： G06F738
CPC分类号： H03K19/17756 , H03K19/17736
摘要： A Variable Grain Architecture (VGA) device includes a shared output component (SOC) that may be used for programmably-routing process result signals onto either or plural ones of differently directed longlines within an FPGA. Plural VGB's make shared use of each SOC to output respective function signals to the longlines. The SOC may be also used for programmably-routing signals (e.g., feedthrough signals) that are selectively acquired from either one of equivalent but differently positioned interconnect channels. Such freedom in routing VGB result signals or feedthrough signals can allow FPGA configuring software to explore a wider range of partitioning, placement and/or routing options for finding optimized implementations in the VGA FPGA device of various, supplied design specifications.
摘要翻译： 可变粒度结构（VGA）设备包括共享输出组件（SOC），其可以用于将处理结果信号可编程地路由到FPGA内的不同定向长线中的一个或多个上。 多个VGB共享使用每个SOC，以将相应的功能信号输出到延绳。 SOC也可用于可编程地路由选择性地从等效但不同位置的互连通道中的任一个获取的信号（例如，馈通信号）。 路由VGB结果信号或馈通信号的这种自由可以允许FPGA配置软件探索更广泛的分区，布局和/或布线选项，以便在各种提供的设计规范的VGA FPGA器件中找到优化的实现。
-
4.发明授权Tileable and compact layout for super variable grain blocks within FPGA device 有权FPGA器件内的超可变晶粒块的平铺紧凑布局
公开(公告)号：US06154051A
公开(公告)日：2000-11-28
申请号：US187689
申请日：1998-11-05
申请人： Bai Nguyen , Om P. Agrawal , Bradley A. Sharpe-Geisler , Jack T. Wong , Herman M. Chang , Giap H. Tran
发明人： Bai Nguyen , Om P. Agrawal , Bradley A. Sharpe-Geisler , Jack T. Wong , Herman M. Chang , Giap H. Tran
IPC分类号： H01L27/02 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17736 , H01L27/0207 , H03K19/1778 , H03K19/17796
摘要： A tileable structure is provided for logic array devices. The tileable structure has a mirror-symmetrical arrangement of sets of logic blocks, common control sections for the logic block sets, surrounding interconnect lines, and switching areas at intersections of the interconnect lines.
摘要翻译： 为逻辑阵列器件提供了可瓦片结构。 可瓦片结构具有逻辑块集合的逻辑对称布置，用于逻辑块集合的公共控制部分，周围互连线以及互连线的交叉处的交换区域。
-
公开(公告)号：US06150842A
公开(公告)日：2000-11-21
申请号：US472645
申请日：1999-12-27
IPC分类号： H03K19/173 , H03K19/177 , H01L25/00
CPC分类号： H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17748 , H03K19/17752 , H03K19/17756 , H03K19/17792 , H03K19/17796 , H01L2924/0002
摘要： A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB's) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUT's) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUT's and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions. Each VGB has a common controls section, a wide-gating section and a carry-propagating section. Each super-VGB has a centrally-shared section of longline drivers that may be accessed from any of the constituent VGB's. A diversified spectrum of interconnect lines, including 2.times.L, 4.times.L, 8.times.L and direct connect surround each super-VGB to provide different kinds of interconnect.
-
6.发明授权Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources 有权用于配置具有可变粒度组件的FPGA以提供对互连资源的时间共享访问的方法公开(公告)号：US06590415B2
公开(公告)日：2003-07-08
申请号：US09841209
申请日：2001-04-23
IPC分类号： G06F738
CPC分类号： H03K19/17736 , H03K19/1737
摘要： A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions. Each CBE may be programmably configured to provide no more than a 2-to-1 dynamic multiplexer (2:1 DyMUX). The dynamically-selectable output of such a synthesized 2:1 DyMUX may then be output onto a shared interconnect line. Pairs of CBE's may be synthetically combined to efficiently define 4:1 DyMUX's with each such 4:1 multiplexer occupying a Configurable Building Block (CBB) structure. Pairs of CBB's may be synthetically combined to efficiently define 8:1 DyMUX's with each such synthesized 8:1 multiplexer occupying a vertically or horizontally-extending leg portion of an L-shaped, VGB structure (Variable Grain Block). The so-configured leg portion of the VGB may then output the signal selected by its 8:1 DyMUX onto a shared interconnect line that is drivable by the VGB leg. Pairs or quartets of VGB's may be synthetically combined to efficiently define higher order, N:1 DyMUX's.
摘要翻译： 可变格式架构（VGA）用于从原始构建元素（CBE）合成每个给定任务的适当量的动态复用能力。 这些可配置构建单元（CBE）的未使用的配置可重新配置以执行更多的逻辑功能来代替动态复用功能。每个CBE可以可编程配置为提供不超过2对1的动态多路复用器（2：1 DyMUX ）。 然后可以将这种合成的2:1 DyMUX的动态可选输出输出到共享互连线上。 CBE的对可以合成，以有效地定义4：1的DyMUX，每个这样的4：1多路复用器占用可配置的构建块（CBB）结构。 CBB的对可以合成组合，以有效地定义8：1 DyMUX，每个这样合成的8：1多路复用器占据L形VGB结构（可变颗粒块）的垂直或水平延伸的腿部分。 然后，VGB的如此配置的腿部分可以将由其8：1 DyMUX选择的信号输出到由VGB支路驱动的共享互连线上。 VGB的对或四重组可以合成组合，以有效地定义高阶N：1 DyMUX。
-
7.发明授权Methods for configuring FPGA's having variable grain blocks and shared logic for providing time-shared access to interconnect resources 失效用于配置具有可变粒度块的FPGA的方法和用于提供对互连资源的时间共享访问的共享逻辑公开(公告)号：US06292930B1
公开(公告)日：2001-09-18
申请号：US09603119
申请日：2000-06-22
IPC分类号： G06F1750
CPC分类号： H03K19/17752 , H03K19/1737 , H03K19/17736
摘要： A Variable Grain Architecture (VGA) includes a shared output component (SOC) that may be used for outputting different signals onto a shared longline within an FPGA. Plural VGB's make shared use of the SOC to out respective function signals to the shared longline.
摘要翻译： 可变晶体结构（VGA）包括可用于将不同信号输出到FPGA内的共享长线上的共享输出组件（SOC）。 多个VGB将共享的SOC用于将相应的功能信号分配给共享的延长线。
-
8.发明授权Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuits 失效FPGA集成电路中可变晶粒块之间的对称，扩展和快速直接连接公开(公告)号：US06275064B1
公开(公告)日：2001-08-14
申请号：US08996361
申请日：1997-12-22
IPC分类号： G06F738
CPC分类号： H03K19/17756 , H03K19/17728 , H03K19/17736 , H03K19/17792 , H03K19/17796
摘要： A Field Programmable Gate Array (FPGA) device includes a plurality of variable grain blocks (VGBs) and a plurality of interconnect lines for providing program-defined routing of signals between the VGBs. The VGBs include a plurality of L-organized CBBs (configurable logic blocks) having function-producing resources. Each CBB includes 6 term inputs, 2 control inputs and one direct connect output. Each CBB includes two configurable building elements having 3 term inputs and 1 control input, respectively. The plurality of interconnect lines includes a direct connect architecture for providing programmably-selectable, dedicated connections between a center VGB, in particular a CBB, and neighboring VGBs. The direct connect architecture and positioning of inputs and outputs enables 1) enhanced flexibility and efficiency in the configuration placement and routing software 2) efficiently emulates random logic nets and 3) reduces many direct connect line wire lengths.
摘要翻译： 现场可编程门阵列（FPGA）装置包括多个可变晶粒块（VGB）和多个互连线，用于在VGB之间提供程序定义的信号路由。 VGB包括具有功能生成资源的多个L组织CBB（可配置逻辑块）。 每个CBB包括6个术语输入，2个控制输入和一个直接连接输出。 每个CBB包括两个可配置的建筑元件，分别具有3个项目输入和1个控制输入。 多个互连线包括用于在中心VGB（特别是CBB）和相邻VGB之间提供可编程选择的专用连接的直接连接架构。 直接连接架构和输入和输出的定位可以实现1）增强配置布局和路由软件的灵活性和效率2）高效地模拟随机逻辑网络，3）减少许多直接连接线路的长度。
-
公开(公告)号：US06621298B2
公开(公告)日：2003-09-16
申请号：US10090209
申请日：2002-03-04
IPC分类号： H03K19094
CPC分类号： H03K19/1737 , H01L2924/0002 , H03K19/17728 , H03K19/17736 , H03K19/17748 , H03K19/17752 , H03K19/17756 , H03K19/17792 , H03K19/17796 , H01L2924/00
摘要： A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB's) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUT's) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUT's and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions. Each VGB has a common controls section, a wide-gating section and a carry-propagating section. Each super-VGB has a centrally-shared section of longline drivers that may be accessed from any of the constituent VGB's. A diversified spectrum of interconnect lines, including 2xL, 4xL, 8xL and direct connect surround each super-VGB to provide different kinds of interconnect.
-
公开(公告)号：US06380759B1
公开(公告)日：2002-04-30
申请号：US09626094
申请日：2000-07-26
IPC分类号： H03K19177
CPC分类号： H03K19/1737 , H01L2924/0002 , H03K19/17728 , H03K19/17736 , H03K19/17748 , H03K19/17752 , H03K19/17756 , H03K19/17792 , H03K19/17796 , H01L2924/00
摘要： A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB's) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUT's) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUT's and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions. Each VGB has a common controls section, a wide-gating section and a carry-propagating section. Each super-VGB has a centrally-shared section of longline drivers that may be accessed from any of the constituent VGB's. A diversified spectrum of interconnect lines, including 2×L, 4×L, 8×L and direct connect surround each super-VGB to provide different kinds of interconnect.
摘要翻译： 公开了一种可变颗粒结构，其中可变颗粒块（VGB）彼此楔形在一起，彼此相反地限定超VGB结构。 超VGB结构被布置为FPGA器件内的矩阵。 每个VGB包括用于通过将先前层的较少复杂功能信号折叠在一起形成更复杂功能信号的渐进功能合成层。 在对应的超VGB结构的外围附近提供包含一组函数产生查找表（LUT）的函数生成层。 在一种情况下，功能产生层是L形的，包括可配置构件的对称分布。 信号采集层与相邻的互连线接口，以获取LUT和控制的输入项。 在信号获取层和功能产生层之间插入解码层，用于提供捆绑和截取功能。 每个VGB有一个共同的控制部分，一个宽门控部分和一个进位传播部分。 每个超级VGB都有一个中心共享的长线驱动程序部分，可以从任何组成的VGB访问。 互联线路的多样化，包括2xL，4xL，8xL和直接连接围绕每个超VGB，以提供不同种类的互连。
-
-
-
-
-
-
-
-
-
搜索结果
91 条记录 (耗时 0.035 秒)
