公开(公告)号：US20080059824A1

公开(公告)日：2008-03-06

申请号：US11469153

申请日：2006-08-31

Applicant: Omid Rowhani ,  Vincent Ross

Inventor： Omid Rowhani ,  Vincent Ross

IPC: H02J1/00 ,  G06F1/00

CPC classification number: H03K17/167 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/171 ,  Y10T307/461

Abstract: A method and apparatus for selectively charging a secondary voltage rail includes selectively and partially charging a secondary voltage rail using at least one soft start power gate switch and using an initial power control indicator. The partially charged secondary voltage rail is selectively charged, using at least one main power gate switch, based on the initial power control indicator and a detected voltage on the secondary voltage rail. When the initial power control indicator is in a state representative of an initial power up command and when the detected voltage is greater than or equal to a predetermined voltage level, at least one main power gate switch is closed thereby charging the secondary voltage rail.

Abstract translation: 用于选择性地对次级电压轨进行充电的方法和装置包括使用至少一个软启动功率门开关并使用初始功率控制指示器来选择性地和部分地对次级电压轨充电。 使用至少一个主电源栅极开关，基于初始功率控制指示器和次级电压轨上的检测电压，选择性地对部分充电的次级电压轨进行充电。 当初始功率控制指示器处于表示初始上电命令的状态下，并且当检测到的电压大于或等于预定电压电平时，关闭至少一个主电源门开关，从而对次级电压轨充电。

公开(公告)号：US08015419B2

公开(公告)日：2011-09-06

申请号：US11469153

申请日：2006-08-31

Applicant: Omid Rowhani ,  Vincent Ross

Inventor： Omid Rowhani ,  Vincent Ross

IPC: G06F1/00 ,  H01L25/00 ,  H03K17/00

CPC classification number: H03K17/167 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/171 ,  Y10T307/461

Abstract: A method and apparatus for selectively charging a secondary voltage rail includes selectively and partially charging a secondary voltage rail using at least one soft start power gate switch and using an initial power control indicator. The partially charged secondary voltage rail is selectively charged, using at least one main power gate switch, based on the initial power control indicator and a detected voltage on the secondary voltage rail. When the initial power control indicator is in a state representative of an initial power up command and when the detected voltage is greater than or equal to a predetermined voltage level, at least one main power gate switch is closed thereby charging the secondary voltage rail.

Abstract translation: 用于选择性地对次级电压轨进行充电的方法和装置包括使用至少一个软启动功率门开关并使用初始功率控制指示器来选择性地和部分地对次级电压轨充电。 使用至少一个主电源栅极开关，基于初始功率控制指示器和次级电压轨上的检测电压，选择性地对部分充电的次级电压轨进行充电。 当初始功率控制指示器处于表示初始上电命令的状态下，并且当检测到的电压大于或等于预定电压电平时，关闭至少一个主电源门开关，从而对次级电压轨充电。

公开(公告)号：US20110115524A1

公开(公告)日：2011-05-19

申请号：US12620042

申请日：2009-11-17

Applicant: Omid Rowhani

Inventor： Omid Rowhani

IPC: H03K19/00

CPC classification number: H03K19/0008 ,  H03K3/012 ,  H03K3/037

Abstract: A disclosed integrated circuit logic cell includes a clock input operative to receive a clock input from a clock tree of the integrated circuit, and clocking circuitry, internal to the logic cell, operative to place a plurality of clock nodes, within the logic cell, in a logical off state in response to a predetermined logic state of the logic cell, thereby preventing the clock nodes from toggling during the predetermined logic state of the logic cell. The integrated circuit logic cell includes primary logic circuitry, internal to the logic cell, operatively coupled to the clocking circuitry which is operatively coupled to an input of the primary logic circuitry. The clocking circuitry provides clock outputs operatively coupled to the clock nodes which are within the primary logic circuitry, and is operative to control the clock outputs in response to the predetermined logic state.

Abstract translation: 所公开的集成电路逻辑单元包括可操作以从集成电路的时钟树接收时钟输入的时钟输入和逻辑单元内部的时钟电路，用于将多个时钟节点放置在逻辑单元内， 响应于逻辑单元的预定逻辑状态的逻辑关闭状态，从而防止时钟节点在逻辑单元的预定逻辑状态期间切换。 集成电路逻辑单元包括逻辑单元内部的主逻辑电路，可操作地耦合到可操作地耦合到主逻辑电路的输入的时钟电路。 时钟电路提供可操作地耦合到主逻辑电路内的时钟节点的时钟输出，并且可操作以响应于预定逻辑状态来控制时钟输出。

公开(公告)号：US08680648B2

公开(公告)日：2014-03-25

申请号：US13156399

申请日：2011-06-09

Applicant: Omid Rowhani ,  Victor M. Ma

Inventor： Omid Rowhani ,  Victor M. Ma

IPC: H01L23/52

CPC classification number: H01L23/522 ,  G06F17/5068 ,  G06F17/5081 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of present invention provide methods and apparatuses for connecting and/or disconnecting nodes in a semiconductor device. Embodiments of the apparatus may include a plurality of metal layers formed above a substrate and an interconnect structure formed between first and second nodes in the plurality of metal layers. The interconnect structure includes one or more metal lines formed in each of the metal layers. The metal lines are connected by a plurality of vias. Modifying one of the metal lines in any one of the metal layers changes an electrical connection between the first and second nodes.

Abstract translation: 本发明的实施例提供了用于在半导体器件中连接和/或断开节点的方法和装置。 该装置的实施例可以包括形成在基板上的多个金属层和形成在多个金属层中的第一和第二节点之间的互连结构。 互连结构包括在每个金属层中形成的一个或多个金属线。 金属线通过多个通孔连接。 改变任何一个金属层中的金属线之一改变了第一和第二节点之间的电连接。

公开(公告)号：US20120313254A1

公开(公告)日：2012-12-13

申请号：US13156399

申请日：2011-06-09

Applicant: Omid Rowhani ,  Victor M. Ma

Inventor： Omid Rowhani ,  Victor M. Ma

IPC: H01L23/522 ,  G06F17/50 ,  H01L21/768

CPC classification number: H01L23/522 ,  G06F17/5068 ,  G06F17/5081 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of present invention provide methods and apparatuses for connecting and/or disconnecting nodes in a semiconductor device. Embodiments of the apparatus may include a plurality of metal layers formed above a substrate and an interconnect structure formed between first and second nodes in the plurality of metal layers. The interconnect structure includes one or more metal lines formed in each of the metal layers. The metal lines are connected by a plurality of vias. Modifying one of the metal lines in any one of the metal layers changes an electrical connection between the first and second nodes.

Abstract translation: 本发明的实施例提供了用于在半导体器件中连接和/或断开节点的方法和装置。 该装置的实施例可以包括形成在基板上的多个金属层和形成在多个金属层中的第一和第二节点之间的互连结构。 互连结构包括在每个金属层中形成的一个或多个金属线。 金属线通过多个通孔连接。 改变任何一个金属层中的金属线之一改变了第一和第二节点之间的电连接。

公开(公告)号：US08269525B2

公开(公告)日：2012-09-18

申请号：US12620042

申请日：2009-11-17

Applicant: Omid Rowhani

Inventor： Omid Rowhani

IPC: H03K19/00

CPC classification number: H03K19/0008 ,  H03K3/012 ,  H03K3/037

Abstract: A disclosed integrated circuit logic cell includes a clock input operative to receive a clock input from a clock tree of the integrated circuit, and clocking circuitry, internal to the logic cell, operative to place a plurality of clock nodes, within the logic cell, in a logical off state in response to a predetermined logic state of the logic cell, thereby preventing the clock nodes from toggling during the predetermined logic state of the logic cell. The integrated circuit logic cell includes primary logic circuitry, internal to the logic cell, operatively coupled to the clocking circuitry which is operatively coupled to an input of the primary logic circuitry. The clocking circuitry provides clock outputs operatively coupled to the clock nodes which are within the primary logic circuitry, and is operative to control the clock outputs in response to the predetermined logic state.

Abstract translation: 所公开的集成电路逻辑单元包括可操作以从集成电路的时钟树接收时钟输入的时钟输入和逻辑单元内部的时钟电路，用于将多个时钟节点放置在逻辑单元内， 响应于逻辑单元的预定逻辑状态的逻辑关闭状态，从而防止时钟节点在逻辑单元的预定逻辑状态期间切换。 集成电路逻辑单元包括逻辑单元内部的主逻辑电路，可操作地耦合到可操作地耦合到主逻辑电路的输入的时钟电路。 时钟电路提供可操作地耦合到主逻辑电路内的时钟节点的时钟输出，并且可操作以响应于预定逻辑状态来控制时钟输出。